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Dive into the research topics where Kyoung-sei Choi is active.

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Featured researches published by Kyoung-sei Choi.


electronic components and technology conference | 2010

Fine-pitch, cost effective flip chip package development: TAB-BGA

Soojeoung Park; Sang-Gui Jo; Ji-Yong Park; Hyon-chol Kim; Kawngjin Bae; Chulwoo Kim; Kyoung-sei Choi; Sa-Yoon Kang

This paper presents a cost effective fine-pitch flip chip solution to meet the increasing demand for the high performance small form factor packages. Tape Automated Bonding (TAB)-BGA package utilizes thermo-compression to bond a flip chip onto a film based substrate instead of reflow soldering. This approach allows for fine-pitch connection that can save significant substrate area, which can be especially cost effective for some package designs that can reduce the conductive layer count from 2 to 1 [1]. For second level interconnects, typical BGA approach was taken for easy adoption. Successfully implementing TAB-BGA has several technical challenges. Applying underfill under the fine-pitch flip chip without creating voids can be difficult. One way to overcome this challenge is by using no filler underfill and overmold type flip chip; however, that can potentially lead to high water absorption rate and delamination issues. Furthermore, board level reliability, especially temperature cycle, can have high failure rate for this type of single layer package structure [2]. To overcome these challenges, flexible PI film based substrate has been used to reduce the residual stress within the package. In addition, Epoxy Molding Compound (EMC) with low modulus at high temperature and solder resist stress buffer layer have been applied to improve the package and board level reliability.


SID Symposium Digest of Technical Papers | 1999

27.3: Improvement of Electrical Stability of Poly-Si TFTs Using Vertical a-Si Offset

Kyoung-Chan Park; Jungheon Yoo; Chi Heon Kim; Moon Ku Han; Kyoung-sei Choi

Polycrystalline silicon (poly-Si) thin film transistors (TFTs) employing vertical amorphous silicon (a-Si) offsets have been fabricated without additional photolithography processes. The a-Si offset has been formed utilizing the poly-Si grain growth blocking effect by thin native oxide film during the excimer laser recrystallization of a-Si. The ON current degradation of the new device after 4 hours electrical stress, was reduced by at least 5 times compared with conventional poly-Si TFTs.


Archive | 2006

CMOS type image sensor module having transparent polymeric encapsulation material

Kyoung-sei Choi


Archive | 2011

Tape for heat dissipating member, chip on film type semiconductor package including heat dissipating member, and electronic apparatus including the same

Kyoung-sei Choi; Byung-Seo Kim; Young-Jae Joo; Ye-Chung Chung; Kyong-soon Cho; Sang-Heui Lee; Si-Hoon Lee; Sa-Yoon Kang; Dae-Woo Son; Sang-Gui Jo; Jeong-kyu Ha; Young-Sang Cho


Archive | 2009

Tape wiring substrates and packages including the same

Yechung Chung; Chulwoo Kim; Eun-Seok Song; Kyoung-sei Choi


Archive | 2011

IMAGE SENSOR CHIP AND CAMERA MODULE HAVING THE SAME

Mi-Na Choi; Kyoung-sei Choi; Hee-Seok Lee; Yong-Hoon Kim; Heejung Hwang; Se-Ran Bae


Archive | 2005

Method for manufacturing tape wiring board

Kyoung-sei Choi; Sa-Yoon Kang; Yong-hwan Kwon; Chung-Sun Lee


Archive | 2011

Semiconductor Devices And Methods Of Controlling Temperature Thereof

Jae Choon Kim; Eunseok Cho; Mi-Na Choi; Kyoung-sei Choi; Heejung Hwang; Se-Ran Bae


Archive | 2005

Method of manufacturing tape wiring substrate

Chung-Sun Lee; Sa-Yoon Kang; Yong-hwan Kwon; Kyoung-sei Choi


Archive | 2004

Flexible substrate for a semiconductor package, method of manufacturing the same, and semiconductor package including flexible substrate

Kyoung-sei Choi

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