KyungOe Kim

Low cost flip chip (LCFC): An innovative approach for breakthrough reduction in flip chip package cost

A new low cost flip chip (LCFC) packaging solution is developed that dramatically reduces flip chip package cost. The solution entails innovations and improvements in the bump, interconnect structure, substrate design and underfilling process. Cu column bumps with solder caps are used to form a “Bump on Lead (BOL)” interconnection with narrow substrate pads with no solder mask confinement (“open solder mask”, or “open SR”) and no solder-on-pad finish (“no SOP”). This results in a substrate design with relaxed design rules despite high I/O escape densities, enabling a majority of IC designs in the sub-1000 pin range to fit in 2-lyr laminate substrates. The novel BOL/open SR/no-SOP interconnect structure is combined with a mold underfilling (MUF) process using high density 1-up matrix substrates to achieve high substrate utilization and low process cost. Furthermore, it is shown through empirical data and FEA modeling that the unique mechanical structure of the BOL interconnection remarkably reduces the stress on Si subsurface layers resulting in elimination of the low K damage phenomenon commonly observed in sub-45 nm Si nodes. The LCFC technology is Pb-free, scalable to very fine pitch in the sub-100 um range and highly electromigration-resistant, providing a natural migration path to 3D/TSV micro bump / micro bond and green solutions for the future. In the present paper, we present in detail, the structure, assembly process and reliability of this packaging solution. We also present data on the application of the solution to advanced sub-45 nm Si nodes with ELK (Extra Low K) dielectrics.

Innovative approaches in flip chip packaging for mobile applications

In this paper we present new approaches in the development of flip chip technology for mobile platforms. We assess the challenges presented by the use of flip chip interconnection as opposed to the traditional approach of wire bonding and present innovative solutions developed to address those challenges. In particular, we describe innovations in the area of routing-efficient interconnection, bumped wafer handling and thinning methods, mold underfill technology, new substrate technology and approaches for Pb-free packaging.

Flip Chip Package-in-Package (fcPiP): A New 3D Packaging Solution for Mobile Platforms

A new chip scale package is developed for use in high end cellular handsets and mobile products. The package houses a Baseband device, a pre-packaged Memory device and an Analog device in a 3-high stacked Package-in-Package (PiP) configuration wherein the base band die is attached to a 4-layer 1-2-1 Build-up laminate substrate using flip chip interconnection and the Memory package and Analog die are interconnected to each other as well as to the substrate using wire bonding. The package represents the ultimate in integration, wiring density, high performance and miniaturization. The development of the package was accomplished through close co-working of multidisciplinary teams comprising packaging, design and device architecture. The paper describes the challenges in the development of the individual packaging technologies such as bumped wafer thinning, thin die flip chip attach and underfilling, low loop wire bonding and the integration of those technologies, such as flip chip and wire bonding on the same substrate, underfill and overmolding, and chip-package interactions in the form of parametric shifts in sensitive analog circuitry on the die. The assembly process, reliability and failure modes observed are described in detail including the eventual qualification of the package and its introduction into volume production.