L. Aguilera

Improving the electrical performance of a conductive atomic force microscope with a logarithmic current-to-voltage converter

A new configuration of conductive atomic force microscope (CAFM) is presented, which is based in a standard CAFM where the typical I-V converter has been replaced by a log I-V amplifier. This substitution extends the current dynamic range from 1-100 pA to 1 pA-1 mA. With the broadening of the current dynamic range, the CAFM can access new applications, such as the reliability evaluation of metal-oxide-semiconductor gate dielectrics. As an example, the setup has been tested by analyzing breakdown spots induced in SiO2 layers.

Development of a conductive atomic force microscope with a logarithmic current-to-voltage converter for the study of metal oxide semiconductor gate dielectrics reliability

A new configuration of conductive atomic force microscope (CAFM) is presented, which is based in a conventional AFM with a logarithmic current-to-voltage (log I-V) amplifier. While a standard CAFM allows to measure a current dynamic range of typically three orders of magnitude (0.1–100pA), with the new setup it is possible to measure up to nine orders of magnitude. The extended current range allows to evaluate the reliability of gate dielectrics in a single electrical test, overcoming the limitations of standard CAFM configurations. The setup has been tested by analyzing breakdown (BD) spots induced in SiO2 and high-k layers. For current measurements, the results show that I-V characteristics and current images (measured at a constant voltage) can be easily obtained in a wide dynamic range, which can reveal new details of the BD mechanisms. In particular, the setup was used to investigate the area electrically affected by the breakdown event in SiO2 and HfO2∕SiO2 stacks.

Influence of vacuum environment on conductive atomic force microscopy measurements of advanced metal-oxide-semiconductor gate dielectrics

Most of the knowledge about the electrical behavior of gate dielectric materials has been gained from measurements performed on macroscopic metal-oxide-semiconductor MOS capacitors or transistors using standard electrical characterization methods at wafer level. Although very important information has been obtained using these methods, they provide spatially averaged information on the electrical properties of the material. On the contrary, conductive atomic force microscopy CAFM allows us to characterize topographically and electrically the gate dielectric with nanometer resolution. The CAFM works on bare gate dielectric surfaces and the CAFM tip plays the role of the metal electrode of a nanometer sized MOS capacitor with an area of few hundreds of nm2. Therefore, these measurements allow us to study the spatial distribution of current throughout the device area and its dependence on the applied voltage. To grant the current flow between the tip and the sample, the CAFM must work in contact mode. Due to that, when scanning in air with the CAFM, some undetermined reaction occurs between the tip and the sample probably related to water and/or hydrocarbons , which can cause loss of conductivity and CAFM resolution. In addition, when carriers are injected from the tip, local anodic oxidation is triggered. All these effects are even worse for high-k devices. To avoid these problems, one possibility could be measuring in con-

Comparison of standard macroscopic and conductive atomic force microscopy leakage measurements on gate removed high-k capacitors

Understanding the origin and mechanism of detrimental local phenomena such as charge trapping, trap assisted tunneling, and breakdown in high-k gate oxides adds to the improvement of refining the layer deposition process. Conductive atomic force microscopy (AFM) is a relatively new technique that is able to visualize these local phenomena. In this work we improve the quality of the comparison between standard macroscopic and conductive AFM (C-AFM) microscopic gate leakage measurements by enabling measurements on the exact same dielectric layers of metal gate high-k capacitors and transistors, using a well tuned gate wet etch process. An agreement in leakage current between both measurement types is obtained. Furthermore, we visualize with C-AFM the location and current magnitude of breakdown spots which were induced by standard macroscopic electrical stress. The ability of investigating the local leakage behavior of real devices as it is shown in this work opens the way to better understand gate leakage m...

Pre- and post-BD electrical conduction of stressed HfO2/SiO2 MOS gate stacks observed at the nanoscale

Abstract In this work, the electrical properties of fresh and stressed HfO 2 /SiO 2 gate stacks have been studied using a prototype of Conductive Atomic Force Microscope with enhanced electrical performance (ECAFM). The nanometer resolution of the technique and the extended current dynamic range of the ECAFM has allowed to separately investigate the effect of the electrical stress on the SiO 2 and the HfO 2 layer of the high-k gate stack. In particular, we have investigated this effect on both layers when the structures where subjected to low and high field stresses.

Improving the electrical performance of a CAFM for gate oxide reliability measurements

A new configuration of conductive atomic force microscope (CAFM) is presented, which is based in a standard CAFM where the typical I-V converter has been replaced by a log I-V amplifier. This substitution extends the current dynamic range from 1-100 pA to 1 pA-1 mA. With the broadening of the. current dynamic range, the CAFM can access new applications, such as the reliability evaluation of metal-oxide-semiconductor gate dielectrics. As an example, the setup has been tested by analyzing breakdown spots induced in ultrathin gate SiO2 layers.

Nanoscale effects of annealing on the electrical characteristics of hafnium based devices measured in a vacuum environment

In this work, a conductive atomic force microscope (C-AFM) built in a vacuum environment has been used to characterize the electrical properties of high k samples. In particular, the effect of the annealing on the electrical characteristics of ALD HfO2 samples has been investigated by this technique.

Improved Characterization of high-k Degradation with Vacuum C-AFM

Local phenomena like trap assisted tunneling and oxide breakdown (BD) in new high-k gate oxides in advanced MOS devices hinder the acquisition of device requirements stated in the International Technology Roadmap for Semiconductors (ITRS). Conductive Atomic Force Microscopy (C-AFM) visualizes these local phenomena by measuring the local tunneling through the dielectric. In the first part of this work we show that the physical composition of surface protrusions, that are produced at sites electrically stressed with C-AFM and that distort the electrical measurements, is oxidized Si. In the second part, we illustrate that C-AFM measurements become more reliable in high vacuum (1e −5 torr ) as surface (oxidized Si protrusions) and tip damage is reduced. Finally, we illustrate good agreement between conventional macroscopic electrical measurements and nanometer-scale C-AFM measurements on normal and gate – removed high-k capacitors, respectively. Moreover, to illustrate the strength of the local tunneling technique, we show the possibility of locating BD spots on a high-k capacitor.

Nanoscale and device level reliability of high-k dielectrics based CMOS nanodevices

In this work, standard device level and nanoscale electrical tests have been carried out to evaluate the influence of the high-k and interfacial SiO2 layers on the degradation of HfO2/SiO2 gate stacks. At device level, the effect of static and dynamic electrical stresses has been investigated to evaluate the influence of the voltage polarity in the degradation of the gate stack. At nanoscale level, a Conductive Atomic Force Microscope (C-AFM) has allowed to separately investigate the effect of the electrical stress on the SiO2 and HfO2 layers. Both kinds of tests show that the SiO2 interfacial layer plays an important role in the degradation and breakdown of high-k gate stacks in CMOS advanced nanodevices.

Nanoscale electrical characterization of HfO/sub 2//SiO/sub 2/ MOS gate stacks with enhanced-CAFM

The conduction and dielectric breakdown (BD) of an ultra-thin HfO/sub 2//SiO/sub 2/ gate stack is studied at the nanoscale. With this purpose, an enhanced conductive atomic force microscope (a CAFM with extended electrical performance) has been developed. Using this new set up, different conduction modes have been observed before BD, which can be masked during standard tests. The study of the BD spots has revealed that, as for SiO/sub 2/, the BD of the stack leads to modifications in the topography images and high conductive spots in the current images.