L. Haspeslagh

11-Megapixel CMOS-Integrated SiGe Micromirror Arrays for High-End Applications

In this paper, we report on the design, fabrication, packaging, and testing of very reliable CMOS-integrated 10-cm2 11-megapixel SiGe-based micromirror arrays on top of planarized six-level metal 0.18-¿m CMOS wafers. The array, which is to be used as a spatial light modulator (SLM) for optical maskless lithography, consists of 8 ¿m × 8 ¿m pixels, which can be individually addressed by an analog voltage to enable accurate tilt angle modulation. Due to very stringent requirements on mounted-die flatness (< 0.01 mrad), the first level packaging of SLM die is done using specially designed SiC holders. To avoid trapped particles between the die and holder, which would jeopardize the flatness spec, special backside cleaning of the dies (less than or equal to one 0.8-¿m particle/cm2) is needed before mounting the SLM die on the holder. To enable this backside cleaning and to avoid front-side particles during dicing, handling, and wire bonding, a temporary waferor zero-level packaging cap, which can be placed and removed at room temperature, was developed. The dynamic white light interferometer measurements of packaged dies showed that 99.5% of the 123 648 mirrors tested are within the spec. In addition, a stable average cupping of below 7 nm, an rms roughness of below 1 nm, and a stable actuation of over 2.5 teracycles are demonstrated.

High-Q torsional mode Si triangular beam resonators encapsulated using SiGe thin film

This paper reports on an SOI-based 20 MHz MEMS torsional resonator, wafer-level packaged using SiGe thin film and hermetically sealed using Al sputtering at 1Pa. The packaged resonators display a high quality factor (220,000) and a low motional resistance (12 k Ω) for low DC bias (1 V). The quality factor remains above 100,000 and the temperature coefficient of frequency (TCf) was measured to be −25ppm/°C and linear over the temperature range of −40 to +140 °C. Successful operation of a CMOS-based oscillator using the MEMS torsional resonator as the frequency determining element was demonstrated.

Above-IC generic poly-SiGe thin film wafer level packaging and MEM device technology: Application to accelerometers

We present an attractive poly-SiGe thin film packaging and MEM (Micro Electro-Mechanical) platform technology for integrating various packaged MEM devices above standard CMOS. The packages, having cavities as large as 1mm2, make use of pillars designed to withstand subsequent molding during 1st level packaging. Covers on top of the release holes avoid deposition inside the cavity during sealing. Hermeticity is proven in vacuum, air and N2 atmosphere and at different temperatures. Packaged functional accelerometers sealed at a pressure around 1bar, have an equivalent performance in measuring accelerations of about 1g compared to a piezoelectric commercial reference device.

CMOS-integrated poly-SiGe cantilevers with read/write system for probe storage device

A poly-SiGe technology enabling a dense array of micro-cantilevers and tips on CMOS is demonstrated. Built from a dual-thickness structural layer, the cantilevers feature a very small initial bending and have a compliant torsional suspension with a stiffness of 3×10−10 Nm/rad. Sharp tips are formed in a low-temperature amorphous silicon layer by isotropic plasma etching. An electrical read/write system is formed by connecting the tip to the CMOS with a suspended platinum trace, running on top of the cantilever.

Poly-SiGe-Based MEMS Thin-Film Encapsulation

This paper presents an attractive poly-SiGe thin-film packaging and MEM (microelectromechanical) platform technology for the generic integration of various packaged MEM devices above standard CMOS. Hermetic packages with sizes up to 1 mm2 and different sealed-in pressures ( ~ 100 kPa and ~ 2 kPa) are demonstrated. The use of a porous cover on top of the release holes avoids deposition inside the cavity during sealing, but leads to a sealed-in pressure of approximately 100 kPa, i.e. atmospheric pressure. Vacuum ( ~ 2 kPa) sealing has been achieved by direct deposition of a sealing material on the SiGe capping layer. Packaged functional accelerometers sealed at around 100 kPa have an equivalent performance in measuring accelerations of about 1 g compared to a piezoelectric commercial reference device. Vacuum-sealed beam resonators survive a 1000 h 85°C/85%RH highly accelerated storage test and 1000 thermal cycles between -40°C and 150°C.

Packaging of 11 MPixel CMOS-Integrated SiGe Micro-Mirror Arrays

This article reports for the first time on the packaging of 10 cm2 11 MPixel SiGe micro-mirror arrays, intended to be used as spatial light modulator (SLM). Due to very stringent requirements on mounted die flatness (≪0.01 mrad), first-level packaging of the SLM die is done using specially designed SiC holders. To avoid trapped particles between die and holder, which would jeopardize the flatness spec, special backside cleaning of the dies (¿ 1 0.8 ¿m particle/cm2) is needed before mounting the SLM die on the holder. To enable this backside cleaning and to avoid front-side particles during dicing, handling and wire bonding, a temporary wafer-level or 0-level packaging cap which can be placed and removed at room temperature was developed. Dynamic white light interferometer measurements of packaged dies showed that 99.5% of 123,648 mirrors tested are within spec.

Stiction-free poly-SiGe resonators for monolithic integration of biosensors with CMOS

This work presents the first fabricated and characterized MEMS in polycrystalline silicon-germanium (poly-SiGe) for biosensing applications. The devices, clamped-clamped microresonators, combine the possibility of above-IC MEMS-CMOS integration with a stiction-free design that enables biomolecule mass sensing in air. By perforating the resonant beam with square or hexagonal holes, a higher surface-to-volume ratio is achieved leading to an increased relative frequency shift for a certain analyte surface density. A minimum detectable mass of ∼2pg in air was calculated. A mass sensing test was performed on these perforated devices by immobilization of biotin and the extraction of the resulting resonance frequency shift.

A wafer-level poly-sige-based thin film packaging technology demonstrated on a soi-based high-Q MEM resonator

This paper reports a 0-level or wafer-level thin film packaging technology for MEMS using polycrystalline silicon-germanium (poly-SiGe) as the base material complemented with a metal seal. Hermetic packages with a cavity pressure below 0.3mbar are demonstrated on a SOI-based torsional-mode Si resonator. Monitoring the quality factor of these resonators revealed that the low pressure is retained for over 6 months while storing at ambient pressure and room temperature. Moreover, the package survived several months under harsh testing conditions with temperatures up to 125°C and 85% relative humidity. This thin film SiGe-based technology has large potential for the on-wafer packaging of a broad range of MEMS devices.

CMOS-integrated sige MEMS: Application to micro-mirrors

SiGe is a very interesting material for integrating MEMS and CMOS in a MEMS-last approach. SiGe layers are, due to their similar crystal structure, very comparable to Si layers: inherently very reliable, high elastic constants and high intrinsic quality factors and they can be processed using similar state-of-the-art tools. All these desired properties can be reached at a deposition temperature which is low enough to allow for post-processing the MEMS layers on top of the IC. As an application example, micro-crystalline SiGe has been used as structural layer for fabricating 10cm2 11 MPixel CMOS-integrated micro-mirror arrays. The array consists of 8 µm × 8 µm pixels which can be individually addressed by an analog voltage to enable accurate tilt angle modulation. A stable average cupping below 7 nm, an RMS roughness below 1 nm and a long lifetime (≫1012 cycles) are demonstrated.

High speed TDI embedded CCD in CMOS sensor

This paper reports on a Time Delay and Integration image sensor System-on-Chip realized in an embedded CCD process. The integration of single-poly CCD modules into a standard 0.13?m CMOS process is discussed. The technology performance has been evaluated using dedicated test structures. Next, a prototype TDI imager with 5?m pixel pitch, 512 rows and 1024 columns was designed, manufactured and characterized. Charge Transfer Efficiency greater than 0.9999 up till very high line rates of 400kHz was recorded.