L.J. Quinn

Polycrystalline silicon film growth in a SiF4/SiH4/H2 plasma

Abstract The growth of polycrystalline silicon (polysilicon) films from SiF 4 /SiH 4 /H 2 gas mixtures is reported. The polysilicon films have been deposited in a multi process reactor by a PECVD process. The effect of r.f. power, chamber temperature and gas flow ratios on grain size and deposition rate have been determined. The fluorine concentration and the grain sizes of the films have been determined by SIMS and atomic force microscopy (AFM), respectively. Grain sizes in excess of 900 A are reported for layers deposited at 300°C.

Plasma-enhanced silicon nitride deposition for thin film transistor applications

The characteristics of silicon nitride films deposited in a multiprocess reactor have been investigated to determine the most suitable layers for dielectric and passivation applications. Process parameters such as rf power, temperature and gas flow ratios have been varied to control the stoichiometry of the films, and associated parameters such as refractive index, BHF etch rate, relative permittivity and breakdown field. Using these results, silicon nitride films with favourable characteristics have been deposited and used successfully in thin film transistors.

Deposition and characterisation of silicon grown in a SiF4/SiH4/H2 mixture for TFT applications

Abstract The growth of polycrystalline silicon (polysilicon) films from SiF4/SiH4/H2 gas mixtures is reported. These silicon films have been deposited on Corning 1737 glass substrates by adding SiF4 to an existing LPCVD polysilicon process in a Multi Process reactor. In addition, polysilicon films have been deposited in the same reactor by a PECVD process. The fluorine concentration was measured by SIMS. Grain size was determined by atomic force microscopy and showed a marked increase with fluorine incorporation.

Enhancement of TFT Performance by Low Temperature Oxygen Annealing

An improvement in the electrical characteristics of TFT’s is evident when the active silicon layer is given a low temperature oxygen anneal prior to the deposition of the gate dielectric. The devices were fabricated using a self-aligned polysilicon gate process on Corning 1737 glass substrates and the maximum processing temperature was 620 °C. The TFT’s exhibit an increase in carrier mobility, from 24.1cm /Vsec to 31.6cm/Vsec, and a reduction in threshold voltage from 12.7V to 9.2V after a 50 hour anneal.

Single crystal silicon on glass

Abstract Electrostatic bonding has been used to create single crystal silicon layers on glass. Etch stop technology is required for the production of thin silicon layers. Implantation of carbon with a dose of 3 E16 cm −2 at 180 keV is shown to be an effective etch stop. Thin silicon layers have been produced with an average thickness of 3996 A and a standard deviation of 191 A across 100 mm diameter glass substrates.

A multi process reactor for low temperature TFT fabrication

A single chamber multi-process reactor has been developed specifically for Thin Film Transistor (TFT) technology. A variety of processes can be performed sequentially in the system with minimum delay between process steps. Processes available at the moment include CVD silicon, plasma enhanced silicon nitride deposition and plasma etching/substrate cleaning. The layers produced to date and the processes available with this machine have been characterised. The individual processes have yielded results comparable to those of single step reactors. All processes developed with this reactor have been limited to 620/spl deg/C to ensure compatibility with Corning 7133 glass substrates. Polysilicon TFTs, with silicon nitride gate dielectrics, have been fabricated with mobilities of 30 cm/sup 2/Vsec and on/off current ratios of >10/sup 6/. The system is best exploited when multi-layer structures are required with minimal contamination. SIMS results of the interface properties are shown for layers deposited sequentially.<<ETX>>

A radiant heated reactor with multistep process capability

Abstract A single chamber multi-process reactor employing a quartz chamber with a radiantly heated graphite susceptor has been developed. A variety of processes can be performed sequentially in the system with minimum delay between process steps. Processes available at present include plasma etching/substrate cleaning, CVD silicon and plasma enhanced silicon nitride deposition. The system has to date been used for fabriacation of thin film transistors at low temperatures for applications on glass substrates. The individual processes have yielded results comparable to those of single step reactors. The system is best exploited when multi-layer structures are required with minimal contamination between layers. Results of SIMS analysis has revealed excellent interface properties between films deposited sequentially in the system.