S.J.N. Mitchell

Characterization of masking materials for deep glass micromachining

In this paper the characterization of different masking materials for the fabrication of flow channels or thin diaphragms in aluminosilicate glass substrates (Corning 1737) is presented. Materials such as photoresist, polysilicon and gold were investigated with concentrated hydrofluoric acid, HF 48% used as an isotropic etchant. The use of single material masks restricts the useable etch depth to less than 250 µm. Surface and material imperfections result in weaknesses in the masking layer and subsequent penetration by the etchant. An etch depth of greater than 300 µ mw as achieved using a combination of thick SU-8 photoresist and polished polycrystalline silicon as the masking material. The two materials act as double protection to the glass substrate and the etch depth obtained is approximately three to six times larger than those published for standard photoresist or SU-8 etch mask.

Polycrystalline silicon film growth in a SiF4/SiH4/H2 plasma

Abstract The growth of polycrystalline silicon (polysilicon) films from SiF 4 /SiH 4 /H 2 gas mixtures is reported. The polysilicon films have been deposited in a multi process reactor by a PECVD process. The effect of r.f. power, chamber temperature and gas flow ratios on grain size and deposition rate have been determined. The fluorine concentration and the grain sizes of the films have been determined by SIMS and atomic force microscopy (AFM), respectively. Grain sizes in excess of 900 A are reported for layers deposited at 300°C.

Plasma-enhanced silicon nitride deposition for thin film transistor applications

The characteristics of silicon nitride films deposited in a multiprocess reactor have been investigated to determine the most suitable layers for dielectric and passivation applications. Process parameters such as rf power, temperature and gas flow ratios have been varied to control the stoichiometry of the films, and associated parameters such as refractive index, BHF etch rate, relative permittivity and breakdown field. Using these results, silicon nitride films with favourable characteristics have been deposited and used successfully in thin film transistors.

Investigation of germanium implanted with hydrogen for layer transfer applications

The technology for thin Ge layer transfer by hydrogen ion-cut process is characterised in this work. Experiments were carried out to determine suitable hydrogen ion implantation doses in germanium for the low temperature ion cut process by examining the formation of blisters on implanted samples. Raman and Spreading Resistance Profiling (SRP) have been used to analyse defects in germanium caused by hydrogen implants. Bevelling has been used to facilitate probing beyond the laser penetration depth. Results of Raman mapping along the projection area reveal that after post implant annealing at 400 °C, some crystal damage remains, while at 600 °C, the crystal damage has been repaired. SRP shows that some amount of hydrogen acceptor states (~1Î1016 acceptors/cm2) remain after 600 °C. These are thought to be vacancy-related point defect clusters.

Deposition and characterisation of silicon grown in a SiF4/SiH4/H2 mixture for TFT applications

Abstract The growth of polycrystalline silicon (polysilicon) films from SiF4/SiH4/H2 gas mixtures is reported. These silicon films have been deposited on Corning 1737 glass substrates by adding SiF4 to an existing LPCVD polysilicon process in a Multi Process reactor. In addition, polysilicon films have been deposited in the same reactor by a PECVD process. The fluorine concentration was measured by SIMS. Grain size was determined by atomic force microscopy and showed a marked increase with fluorine incorporation.

The manufacture of silicon power devices using welding techniques

Abstract Epitaxial growth using chemical vapour deposition is the conventional manner for producing lightly doped silicon on more heavily doped substrates. With this technique it is difficult to achieve thick defect-free layers with high resistivity, and for interdigitated buried gate structure autodoping is a problem. A simpler and less expensive approach is the bonding together of two silicon wafers. The method employed is to polish the silicon surfaces to a roughness of less than 50 nm and to bring them together in a dust-free environment. In the present work, the wafers are cleaned, then washed and brought together in the wash bath to ensure minimum contamination. The bonded wafers are capable of withstanding all normal processing conditions, p-n diodes have been fabricated successfully with near ideal characteristics, and n-p-n bipolar transistors have been produced with the bonded interface in the p-base region. Whilst the density of recombination/generation centres at the bonded interface was around 5 × 1011 cm−2 the average lifetime for minority carriers was 5 μs. By the addition of a p-type layer to the n-p-n transistors, gate turn-off thyristors have been produced successfully.

Enhancement of TFT Performance by Low Temperature Oxygen Annealing

An improvement in the electrical characteristics of TFT’s is evident when the active silicon layer is given a low temperature oxygen anneal prior to the deposition of the gate dielectric. The devices were fabricated using a self-aligned polysilicon gate process on Corning 1737 glass substrates and the maximum processing temperature was 620 °C. The TFT’s exhibit an increase in carrier mobility, from 24.1cm /Vsec to 31.6cm/Vsec, and a reduction in threshold voltage from 12.7V to 9.2V after a 50 hour anneal.

Single crystal silicon on glass

Abstract Electrostatic bonding has been used to create single crystal silicon layers on glass. Etch stop technology is required for the production of thin silicon layers. Implantation of carbon with a dose of 3 E16 cm −2 at 180 keV is shown to be an effective etch stop. Thin silicon layers have been produced with an average thickness of 3996 A and a standard deviation of 191 A across 100 mm diameter glass substrates.

Electrical and Optical Characterization of GeON Layers with High-ĸ Gate Stacks on Germanium for Future MOSFETs

Germanium is an attractive channel material for MOSFETs because of its higher mobility than silicon. GeON is one of the best dielectric candidates on germanium, because it is known to stabilize germanium surfaces. In addition to its improved thermal and chemical stability over the oxides (GeO and GeO2), it was also found that nitridation of germanium surfaces prior to high-k film deposition is effective in suppressing Ge diffusion in metal oxides and leads to improved performance of Ge-based devices. In this paper, GeON has been investigated as an interfacial layer for high-κ gate stacks. Thermally grown GeON layers have been prepared at 550C and compared with plasma GeON layers prepared at 300C. FTIR spectroscopy and spectroscopic ellipsometry were used to characterise the GeON layers. MOS capacitors have been fabricated using both types of GeON with a 20 nm ALD high-κ dielectric (either Al2O3 or HfO2) on top. Electrical properties and thermal stability have been tested up to 350C. Thermal GeON layers were grown by a 2-step process; oxidation at 550C in a dilute O2 ambient followed by nitridation in an NH3 ambient at the same temperature. Plasma GeON layers were prepared using a 40 W N2 plasma treatment following an ex-situ HF treatment. FTIR spectroscopy for the thermal GeON layers (Figure 1) revealed that the initial GeO2 layer is completely converted to GeON during the nitridation step. The GeON peak at 800 cm is in agreement with the studies of Hymes et al. FTIR spectroscopy did not identify any strong evidence of GeON bonding in the very thin plasma-grown samples. Spectroscopic ellipsometry was used to determine thicknesses for the thermal GeON layers in the range 16-20 nm and for the plasma GeON layers of typically 3 nm. The optical band gap of thermally-grown GeON was also determined by spectroscopic ellipsometry to be 4.86 eV, intermediate between the GeO2 and Ge3N4 values quoted by G.Lucovsky. Electrical characterization of the MOS capacitors (see Figure 2) has yielded interface state densities (Dit) of less than 10 cmeV for all devices using the conductance method. The thermal GeON interface layers exhibit low hysteresis (120 mV), whilst the plasma GeON interface layers require a 350C N2 anneal to reduce the hysteresis to 180 mV. Overlying Al2O3 high-κ dielectrics are thermally stable to 350C, whilst HfO2 high-κ dielectrics are stable up to 300C. Figure 1: FTIR studies of thermally grown GeON

Germanium Bonding to AL2O3

Germanium has attractive properties such as high carrier mobility, compatibility with high-K dielectrics, lattice matched for GaAs growth. Germanium on insulator (GOI)(1,2) offers the advantages of germanium and combines them with those of silicon on insulator (SOI). In this work germanium bonding to alumina (AL2O3) is discussed. This platform has added advantages such as thermal matching between the AL2O3 and the germanium substrates, allowing temperatures above 600C to be used without cracking occurring in Ge layer. AL2O3 also offers lower substrate losses than standard SOI and better crosstalk suppression(3). Single crystal AL2O3 , in the form of sapphire, and fine grain AL2O3 have been investigated as possible handle substrates. The single crystal AL2O3 layer employed was Cplane sapphire with an epi ready polished surface. The thickness of the sapphire was 500μm and the surface roughness was measured by white light interferometery to be 0.85nm. The germanium substrates were Umicore produced (100) substrates 500μm thick. Figure 1 shows the bond interface of a silicon dioxide coated germanium substrate bonded to sapphire after the bonded pair had received a bond strengthening anneal at 500 C for 120mins. This image is an optical photograph taken through the transparent sapphire substrate. The thermal coefficient of expansion match between the sapphire substrate and germanium allows higher temperature annealing without cracking of the germanium layer. Sapphire substrates can be expensive costing up to