Douglas G. Mitchell

Implementation of a mobile phone module with redistributed chip packaging

The redistributed chip packaging is an embedded chip technology that eliminates the need for wirebonds and flip chip bumps. This technology enables smaller packages at a lower cost, while providing improved mechanical, electrical and thermal performance. The process involves producing panels placing the chip active face down along with an embedded ground plane (EGP) and screen printing encapsulant to embed the die. Subsequently alternate layers of dielectric and Cu metallization are built up and the packages are sawn into individual units. The use of wafer fabrication tools enables finer lines and spaces in the build-up layers. This paper will discuss process conditions during the panelization and the integration of the base function of an i.275 GSM/EDGE mobile phone into a single module measuring a maximum of 1 square inch. The design of the EGP and the role of simulations to achieve a robust, reliable package will also be discussed. The outputs included moisture sensitivity level (MSL) 3 testing, air-to-air thermal cycling (- 40C/125C) and unbiased highly accelerated stress testing (HAST). Testing of RCP packages will also be discussed.

Engineering nano interfacial layers for low contact resistance in chip to package interconnects

This paper presents a study on the contact resistance of interconnects between chip and package of embedded chip technology. Multi-layered aluminum/titanium tungsten/copper interconnects (Al/TiW/Cu) were used as the model system. Design of experiment was carried out to characterize the effect of under bump metallurgy deposition steps, including the degas and radio frequency (RF) plasma etch steps, on contact resistance. A minimum level of degassing is needed, but the resistance was significantly affected by the amount of RF etch. Extensive failure analysis was done using focus ion beam (FIB), Auger electron spectroscopy (AES), scanning electron microscope (SEM), high resolution transmission electron microscope (HRTEM), and secondary ion mass spectroscopy (SIMS) to correlate the resistance to the quality of the bond pad surface and its interface with overlying TiW/Cu under bump metallurgy layers. With a carefully engineered solution, the contact resistance of aluminum/titanium tungsten/copper interconnects between chip and package was reduced almost 3 orders of magnitude to 10 milliohm range. FIB, SEM, AES, HRTEM, and SIMS were used to characterize the nano interfacial layers of both high contact resistance and low contact resistance samples. HRTEM showed the presence of a distinct interfacial layer between TiW and Al interface for both high and low resistance samples, which has not been reported before. The thickness and composition were characterized using SIMS and HRTEM. The macroscopic resistance characteristics were correlated to the state of the interface as established by SIMS and HRTEM.

Characterization of low alpha emissivity system on electroplated solder bumps

As attention to System Soft Error Rate (SSER) grows, better semiconductor design guidelines are being created. To protect sensitive transistor nodes from alpha particles emanating from trace amounts of natural occurring radioisotopes, improved shielding materials such as die coat barrier films are being used. In parallel, the demand for lower alpha emissivity materials is growing, such that semiconductor materials suppliers and packaging groups must certify their materials as being of a certain alpha emissive content. To this end, this alpha detection system continues to gain prominence, with detection capabilities down to 0.001 alpha count/cm/sup 2//hour and sample measurement sizes to 1000 square centimeters. This study outlines a method of characterization and determines capability of the continuous gas flow proportional counter.