Jungwook Yang

SiGe BiCMOS integrated circuits for high-speed serial communication links

Considerable progress has been made in integrating multi-Gb/s functions into silicon chips for data- and telecommunication applications. This paper reviews the key requirements for implementing such functions in monolithic form and describes their implementation in the IBM SiGe BiCMOS technology. Aspects focused on are the integration of 10-13-Gb/s serializer/deserializer chips with subpicosecond jitter performance, the realization of 40-56-Gb/s multiplexer/demultiplexer functions and clock-and-data- recovery/clock-multiplier units, and, finally, the implementation of some analog front-end building blocks such as limiting amplifiers and electro-absorption modulator drivers. Highlighted in this paper are the key challenges in mixed-signal and analog integrated circuit design at such ultrahigh data rates, and the solutions which leverage high-speed and microwave design and broadband SiGe technologies.

A single-chip 12.5 Gbaud transceiver for serial data communication

A fully integrated single-chip SiGe BiCMOS 12.5 Gbaud serializer/deserializer operates with sub-picosecond PLL jitter and error rates below 5e-14 with both transmit and receive channels active. The chip includes a 12.5 GHz clock multiplier, a 12.5 Gbaud clock and data recovery circuit, a 16:1 multiplexer, 1:16 demultiplexer, and integrated test features. The die area is 6.1 mm/spl times/6.1 mm and consumes 3.3 W from a 3.3 V supply in normal operating mode.

A 3.3-V, 500-Mb/s/ch parallel optical receiver in 1.2-/spl mu/m GaAs technology

A 20-channel parallel optical receiver has been developed that achieves the data transfer rate of 1 GByte/s. Each channel takes a dc-coupled optical input and can be driven by a 250 MHz clock to have a data rate of 500 Mb/s/channel. This parallel optical receiver IC is an integral part of a low cost optical bus technology which was demonstrated to be cost competitive with copper interconnect technology. The power supply is 3.3 V to be compatible with system supply. The control inputs are CMOS logic compatible and data outputs are compatible with IEEE low-voltage differential signals. The chip has been fabricated in a 1.2 /spl mu/m GaAs MESFET technology.

A 3.3 V 20-channel 500 Mb/s/ch optical receiver with integrated optical detectors in 1.2 mm GaAs

System area networks (SAN) for clustered computer system architecture allow flexible growth with lower cost. SANs require high-interconnect bandwidth and long interframe distances and smaller cable bulk. Copper wire technology is beginning to show limitations in signal integrity, cost, and size. For optical interconnects to displace copper, low-cost technology is critical. Optical fiber links using large core multimode step index fiber and plastic leadframe packaging are cost-competitive with copper but present a unique set of challenges for the supporting circuits. This 3.3 V 20-channel optical receiver is for use in a low cost optical link.