Lars Aspemyr

A 9–31-GHz Subharmonic Passive Mixer in 90-nm CMOS Technology

A subharmonic down-conversion passive mixer is designed and fabricated in a 90-nm CMOS technology. It utilizes a single active device and operates in the LO source-pumped mode, i.e., the LO signal is applied to the source and the RF signal to the gate. When driven by an LO signal whose frequency is only half of the fundamental mixer, the mixer exhibits a conversion loss as low as 8-11 dB over a wide RF frequency range of 9-31GHz. This performance is superior to the mixer operating in the gate-pumped mode where the mixer shows a conversion loss of 12-15dB over an RF frequency range of 6.5-20 GHz. Moreover, this mixer can also operate with an LO signal whose frequency is only 1/3 of the fundamental one, and achieves a conversion loss of 12-15dB within an RF frequency range of 12-33 GHz. The IF signal is always extracted from the drain via a low-pass filter which supports an IF frequency range from DC to 2 GHz. These results, for the first time, demonstrate the feasibility of implementation of high-frequency wideband subharmonic passive mixers in a low-cost CMOS technology

Low-power voltage-controlled oscillators in 90-nm CMOS using high-quality thin-film postprocessed inductors

Wafer-level packaging (WLP) technology offers novel opportunities for the realization of high-quality on-chip passives needed in RF front-ends. This paper demonstrates a thin-film WLP technology on top of a 90-nm RF CMOS process with one 15-GHz and two low-power 5-GHz voltage-controlled oscillators (VCOs) using a high-quality WLP or above-IC inductor. The 5-GHz VCOs have a power consumption of 0.33 mW and a phase noise of -115 dBc/Hz and -111 dBc/Hz at 1-MHz offset, respectively, and the 15-GHz VCO has a phase noise of -105 dBc/Hz at 1-MHz offset with a power consumption of 2.76 mW.

A 15 GHz and a 20 GHz low noise amplifier in 90 nm RF-CMOS

The design and measured performance of two low-noise amplifiers at 15 GHz and 20 GHz realized in a 90 nm RF-CMOS process are presented in this work. The 15 GHz LNA achieves a power gain of 12.9 dB, a noise figure of 2.0 dB and an input referred third-order intercept point (IIP3) of -2.3 dBm. The 20 GHz LNA has a power gain of 8.6 dB, a noise figure of 3.0 dB and an IIP3 of 5.6 dBm. Compared to previously reported designs, these two LNAs show lower noise figure at lower power consumption

Low Phase Noise sub-1 V Supply 12 and 18 GHz VCOs in 90 nm CMOS

Two low phase noise, sub-1 V supply VCO topologies have been explored at 12 and 18 GHz in a 90 nm CMOS technology for direct LO generation in microwave link applications. At 12 GHz, a cross-coupled differential NMOS pair VCO achieves a phase noise of -117 dBc/Hz at 1 MHz offset while consuming only 1.6 mW from a 0.47 V supply. At 18 GHz a Hartley VCO with a novel tuning scheme reached -119 dBc/Hz at 1 MHz offset, consuming 4.2 mW from a 0.8 V supply. The well established VCO FOM is 196 and 199 for the 12 and 18 GHz VCOs, respectively

25 GHz and 28 GHz Wide Tuning Range 130 nm CMOS VCOs with Ferroelectric Varactors

Two 130nm CMOS VCOs with ferroelectric varactors are presented. The cross-coupled VCO-cores are flip-chip mounted on silicon carriers with integrated inductors and tunable ferroelectric varactors. The output frequency of the first VCO is tunable from 23.4 GHz to 26.1 GHz, corresponding to a tuning range of 11 %. The phase noise of this VCO, tuned to its center frequency, measures -117 dBC/Hz at 1 MHz offset and the power consumption is 18 mW. The second VCO is tunable from 25.8 GHz to 30.5 GHz, corresponding to a tuning range of 17 %. The phase noise at center frequency for this design measures -109 dBc/Hz and the power consumption is 5.3 mW.

A 5.8 GHz 1.7 dB NF fully integrated differential low noise amplifier in CMOS

This work presents a fully integrated differential 5.8 GHz low-noise amplifier (LNA). The LNA is fabricated in a 90 nm RF-CMOS process and has a power gain of 12.5 dB, an IIP3 of 4dBm, and a noise figure of 1.7 dB consuming 14 mA from a 1.2 V supply. Compared to previously reported differential CMOS designs this LNA show lower noise figure and better linearity.

A 5-25 GHz high linearity, low-noise CMOS amplifier

A very wide-band amplifier has been designed in a 90 nm CMOS process, utilizing a common source topology with shunt resistor-inductor feedback. Both input and output return loss was better than 10 dB from 6 to 23 GHz for a one-stage amplifier and from 5 to 26 GHz for a two-stage version. The gain varied from 6 to 9 dB for the one-stage amplifier and from 12 to 16 dB for the two-stage amplifier over that frequency range. The noise figure is below 7 dB over 5-26 GHz for both amplifiers. At 20 GHz the input IP3 of the one- and two-stage amplifiers were 14 dBm and 6 dBm, respectively

A 20 GHz sub-1V low noise amplifier and a resistive mixer in 90 nm CMOS technology

A 20 GHz sub-1 V low noise amplifier and a resistive mixer are designed and fabricated in 90 nm CMOS technology. The LNA achieves a good linearity along with a moderate gain and noise figure. For instance, at 0.9 V supply voltage, 8.8 dB of gain and 5.2 dB of noise figure, as well as 7.0 dBm of IIP3 are obtained. This LNA can work properly even at a supply voltage as low as 0.66 V. It achieves 8.0 dB of gain, 5.3 dB of noise figure, and 3.8 dBm of III3. The DC consumption is 16.8 mW and 11 mW for a supply voltage of 0.9 V and 0.66 V, respectively. This is the first report of a high frequency CMOS LNA operating at such low supply voltage and low DC power dissipation. Moreover, a 20 GHz resistive passive mixer is presented, exhibiting a high IIP3 of 19 dBm, a moderate conversion loss of 7.6 dB, and a low noise figure of 4.35 dB. It consumes no DC power. Thus, these two circuits are suitable to be applied in a high frequency CMOS front-end operating with sub-1 V supply.

Circuits and system simulations for 100Gb/s optical SCM transmission

The SIAM Medea+ project is developing circuits for 100Gbit/s optical communications for use in the next generation Ethernet backbone network. One promising bandwidth-efficient technology is sub-carrier multiplexing (SCM) where quadrature modulated (QAM) signals on different carrier frequencies are combined and subsequently encoded onto an optical carrier. This transceiver approach capitalizes on the increasing speed of silicon technology to perform more of the signal processing in the electrical domain before converting to light. An advanced 65nm CMOS process on HR-SOI substrate will be evaluated for use in implementing the electrical SCM transmitter and receiver suitable for 100Gbit/s transmission. The authors will present the development of a SCM transceiver link model within AWRs Virtual System Simulation (VSS) environment. This model allows the influence of component performance in the electrical domain, particularly non-linearity and noise, to be assessed with respect to the SCM link performance requirements. The design of critical component building blocks in the 65nm CMOS SOI process such as IQ modulators, power combiners and LNAs for the SCM transceiver will be presented. The performance of these components is then assessed in the system simulation environment to investigate the capabilities of CMOS for next generation optical networking with the SCM architecture.

Third-order nonlinearity vs. load impedance for CMOS low-noise amplifiers

The linearity of two 90nm CMOS low-noise amplifiers has been measured and analyzed. The analysis is based on Taylor series expansion of simulated I-V characteristics. The two amplifiers are cascode amplifiers with transistors of the same size but with different loads. Even though the center frequencies of the amplifiers are as high as 15 and 20GHz, respectively, the measured results correlate well with the low-frequency-based estimation of linearity. The analysis shows that for a low load impedance, the dominating source of nonlinearity is transconductance, while for a high load impedance the nonlinearity of the output conductance instead dominates.