Mattias Ferndahl

60 GHz Single-Chip Front-End MMICs and Systems for Multi-Gb/s Wireless Communication

Single-chip 60 GHz transmitter (TX) and receiver (RX) MMICs have been designed and characterized in a 0.15mum (fT~ 120 GHz/f MAX> 200 GHz) GaAs mHEMT MMIC process. This paper describes the second generation of single-chip TX and RX MMICs together with work on packaging (e.g., flip-chip) and system measurements. Compared to the first generation of the designs in a commercial pHEMT technology, the MMICs presented in this paper show the same high level of integration but occupy smaller chip area and have higher gain and output power at only half the DC power consumption. The system operates with a LO signal in the range of 7-8 GHz. This LO signal is multiplied in an integrated multiply-by-eight (X8) LO multiplier chain, resulting in an IF center frequency of 2.5 GHz. Packaging and interconnects are discussed and as an alternative to wire bonding, flip-chip assembly tests are presented and discussed. System measurements are also described where bit error rate (BER) and eye diagrams are measured when the presented TX and RX MMICs transmits and receives a modulated signal. A data rate of 1.5 Gb/s with simple ASK modulation was achieved, restricted by the measurement setup rather than the TX and RX MMICs. These tests indicate that the presented MMICs are especially well suited for transmission and reception of wireless signals at data rates of several Gb/s

Development of 60-GHz front-end circuits for a high-data-rate communication system

Recent results from a Swedish program for development of 60-GHz monolithic microwave integrated circuits (MMICs) for high-data-rate communication links are presented. Front-end circuits such as mixers, amplifiers, frequency multipliers, IF amplifiers with gain control, and voltage-controlled oscillators (VCOs) have been realized utilizing GaAs PHEMT and MHEMT technologies. A newly developed 7.5-GHz coupled Colpitt VCO shows a minimum phase noise of -95 dBc at 100 kHz offset. A second-harmonic 14-GHz VCO shows a minimum phase noise of less than -90 dBc at 100 kHz. A novel balanced 7-28-GHz MMIC frequency quadrupler is described and compared with a single-ended quadrupler at the same input frequencies. To demonstrate its feasibility and potential application, the quadrupler is combined with the Colpitt VCO and the output characteristics of the resulting 30-GHz MMIC source are measured. A three-stage MHEMT wide-band amplifier covering 43-64 GHz with a gain of 24 dB, a minimum noise figure of 2.5 dB, and a passband ripple of 2 dB is also described. In future 60-GHz systems for mass markets where cost is of utmost importance, Si-based technologies, especially CMOS, are highly interesting. Some recent circuit results based on a 90-nm CMOS technology are also reported.

90 nm CMOS MMIC amplifier

Small signal amplifiers at 20 and 40 GHz, based on a 90 nm CMOS process are demonstrated. A gain of 5.8 dB at 20 GHz for single stage has been obtained with a 1 dB compression point at 1 dBm. The corresponding figures for the 40 GHz amplifiers are 6 dB and -5.75 dBm. Noise figure for the 20 GHz amplifier is 6.4 dB. Both single gate access and double gate access transistors have been used in the design. DC power consumption of the 20 GHz single stage amplifier was found to be 10 mW whereas for the 40 GHz double stage amplifier it is approximately 19 mW. Total circuit area is 0.7/spl times/0.8 mm/sup 2/ for the single stage and 1/spl times/0.7 mm/sup 2/ for the 40 GHz double stage amplifier.

Fully integrated 60-GHz single-ended resistive mixer in 90-nm CMOS technology

This letter presents the design and characterization of a fully integrated 60-GHz single-ended resistive mixer in a 90-nm CMOS technology. A conversion loss of 11.6dB, 1-dB compression point of 6dBm and IIP3 of 16.5dBm were measured with a local oscillator (LO) power of 4dBm and zero drain bias. The possibility of improvement in IIP3 with selective drain bias has been verified. A 3-dB improvement in IIP3 was obtained with 150-mV dc voltage applied at the drain. Microstrip transmission lines are used to realize matching and filtering at LO and radio frequency ports

Balanced Colpitt oscillator MMICs designed for ultra-low phase noise

Balanced voltage-controlled oscillator (VCO) monolithic microwave integrated circuits (MMICs) based on a coupled Colpitt topology with a fully integrated tank are presented utilizing SiGe heterojunction bipolar transistor (HBT) and InGaP/GaAs HBT technologies. Minimum phase noise is obtained for all designs by optimization of the tank circuit including the varactor, maximizing the tank amplitude, and designing the VCO for Class C operation. Fundamental and second harmonic VCOs are evaluated. A minimum phase noise of less than -112 dBc at an output power of 5.5 dBm is achieved at 100-kHz carrier offset and 6.4-GHz oscillation frequency for the fundamental InGaP/GaAs HBT VCO. The second harmonic VCO achieves a minimum measured phase noise of -120 dBc at 100 kHz at 13 GHz. To our best knowledge, this is the lowest reported phase noise to date for a varactor-based VCO with a fully integrated tank. The fundamental frequency SiGe HBT oscillator achieves a phase noise of -108 dBc at 100 kHz at 5 GHz. All MMICs are fabricated in commercial foundry MMIC processes.

40 and 60 GHz frequency doublers in 90-nm CMOS

The design and characterization of both a 40 GHz and a 60 GHz frequency doublers in 90-nm CMOS technology is presented. Conversion loss of 15.8 dB at 40 GHz output frequency with 3 dBm input power and 15.3 dB at 60 GHz with 5 dBm input power was achieved for the two frequency doublers. The power consumption was about 4 mW for both designs.

A General Statistical Equivalent-Circuit-Based De-Embedding Procedure for High-Frequency Measurements

A general equivalent-circuit-based method for the de-embedding of scattering parameters is presented. An equivalent circuit representation is used to model the embedding package. The parameters in the models are estimated with a statistical method using measured data from all de-embedding standards jointly together. Hence, it is possible to assess parameter estimates and their variance and covariance due to measurement uncertainties. A general de-embedding equation, which is valid for any five-port with a defined nodal admittance matrix, is derived and used in the subsequent de-embedding of measured device data. Different equivalent circuit models for the embedding network are then studied, and tradeoffs between model complexity and uncertainty are evaluated. Furthermore, the influence of varying number and combinations of de-embedding standards on the parameter estimates is investigated. The method is verified, using both measured and synthetic data, and compared against previously published work. It is found to be more general while keeping or improving accuracy.

A 15 GHz and a 20 GHz low noise amplifier in 90 nm RF-CMOS

The design and measured performance of two low-noise amplifiers at 15 GHz and 20 GHz realized in a 90 nm RF-CMOS process are presented in this work. The 15 GHz LNA achieves a power gain of 12.9 dB, a noise figure of 2.0 dB and an input referred third-order intercept point (IIP3) of -2.3 dBm. The 20 GHz LNA has a power gain of 8.6 dB, a noise figure of 3.0 dB and an IIP3 of 5.6 dBm. Compared to previously reported designs, these two LNAs show lower noise figure at lower power consumption

The Matrix Balun—A Transistor-Based Module for Broadband Applications

In this paper the analysis and design of a new active balun with very broadband performance, the matrix balun, are reported. Measured results show a common mode rejection ratio, CMRR, larger than 15 dB between 4 and 42 GHz while exhibiting 2 dB single-ended gain with a ripple of 1 dB. The balun was realized in a 0.15 mum GaAs mHEMT process. It occupies a chip area of 0.63 mm2 and consumes a dc power of 20 mW. The same matrix balun circuit may also be biased for amplification and used as a matrix amplifier. The circuit then exhibits 10.5 dB gain up to 63 GHz with 1 dB ripple above 5.5 GHz and a power consumption of 67 mW.

CMOS MMICs for microwave and millimeter wave applications

Recent results on MMIC based on a 90-nm CMOS process are presented. Linear and nonlinear models were developed for the transistors based on S-parameters, noise parameters, and power spectrum measurements. Based on EM-simulations, models for multilayer capacitances, MIM-capacitances, various transmission lines etc were also developed. Amplifiers, frequency mixers, and frequency multipliers were then designed, fabricated and characterized. Amplifiers with a gain of 6 and 3.5 dB per stage at 20 and 40 GHz respectively, were demonstrated as well as frequency multipliers from 20 to 40 GHz with 15.8 dB conversion loss, and 30 to 60 GHz multipliers with 15.3 dB conversion loss. Resistive mixers at 20, 40, and 60 GHz were also demonstrated with promising results.