Mingquan Bao

A 9–31-GHz Subharmonic Passive Mixer in 90-nm CMOS Technology

A subharmonic down-conversion passive mixer is designed and fabricated in a 90-nm CMOS technology. It utilizes a single active device and operates in the LO source-pumped mode, i.e., the LO signal is applied to the source and the RF signal to the gate. When driven by an LO signal whose frequency is only half of the fundamental mixer, the mixer exhibits a conversion loss as low as 8-11 dB over a wide RF frequency range of 9-31GHz. This performance is superior to the mixer operating in the gate-pumped mode where the mixer shows a conversion loss of 12-15dB over an RF frequency range of 6.5-20 GHz. Moreover, this mixer can also operate with an LO signal whose frequency is only 1/3 of the fundamental one, and achieves a conversion loss of 12-15dB within an RF frequency range of 12-33 GHz. The IF signal is always extracted from the drain via a low-pass filter which supports an IF frequency range from DC to 2 GHz. These results, for the first time, demonstrate the feasibility of implementation of high-frequency wideband subharmonic passive mixers in a low-cost CMOS technology

A 15 GHz and a 20 GHz low noise amplifier in 90 nm RF-CMOS

The design and measured performance of two low-noise amplifiers at 15 GHz and 20 GHz realized in a 90 nm RF-CMOS process are presented in this work. The 15 GHz LNA achieves a power gain of 12.9 dB, a noise figure of 2.0 dB and an input referred third-order intercept point (IIP3) of -2.3 dBm. The 20 GHz LNA has a power gain of 8.6 dB, a noise figure of 3.0 dB and an IIP3 of 5.6 dBm. Compared to previously reported designs, these two LNAs show lower noise figure at lower power consumption

Low Phase Noise sub-1 V Supply 12 and 18 GHz VCOs in 90 nm CMOS

Two low phase noise, sub-1 V supply VCO topologies have been explored at 12 and 18 GHz in a 90 nm CMOS technology for direct LO generation in microwave link applications. At 12 GHz, a cross-coupled differential NMOS pair VCO achieves a phase noise of -117 dBc/Hz at 1 MHz offset while consuming only 1.6 mW from a 0.47 V supply. At 18 GHz a Hartley VCO with a novel tuning scheme reached -119 dBc/Hz at 1 MHz offset, consuming 4.2 mW from a 0.8 V supply. The well established VCO FOM is 196 and 199 for the 12 and 18 GHz VCOs, respectively

A Highly Integrated Chipset for 40 Gbps Wireless D-Band Communication Based on a 250 nm InP DHBT Technology

A highly integrated chipset comprising a transmitter (TX) and a receiver (RX) chip, based on a 250 nm InP DHBT technology for high data rate D-band (110-170 GHz) wireless communication is described. The chipset is designed for point-to-point wireless communication for 4G and 5G mobile communication infrastructure, high data rate backhaul, low-latency wireless HDTV transmission and >40 Gbps transmission over dielectric waveguide. The measured RX conversion gain is 26 dB, with a noise figure of 9 dB. The measured TX conversion gain is 20 dB. A maximum QPSK data rate of 44 Gbps is demonstrated, which exceeds the present state-of-the art in the D-band by a factor of 2.

23GHz front-end circuits in SiGe BiCMOS technology

This paper reports a monolithic 23GHz low-noise converter (LNC) and its blocks implemented in commercial SiGe BiCMOS process featuring 70GHz f/sub T/ and 90GHz f/sub max/. In general, measurement and simulation show close correspondence. For low-noise amplifier, 43dB noise figure (NF) and 22dB gain are typically obtained. For mixers, 13.5-15.5dB single sideband NF, 2-6dB gain and 2-8dBm IIP3 are measured, depending on whether or not linearizer is applied. The LNC converts an RF signal around 23GHz down to an IF of 1GHz. Its performance is described and related questions are discussed at the end of this paper.

A 5.8 GHz 1.7 dB NF fully integrated differential low noise amplifier in CMOS

This work presents a fully integrated differential 5.8 GHz low-noise amplifier (LNA). The LNA is fabricated in a 90 nm RF-CMOS process and has a power gain of 12.5 dB, an IIP3 of 4dBm, and a noise figure of 1.7 dB consuming 14 mA from a 1.2 V supply. Compared to previously reported differential CMOS designs this LNA show lower noise figure and better linearity.

MMIC-oscillator designs for ultra low phase noise

Various balanced VCO-topologies like cross-connected (negative gm), coupled cross-connected, coupled Colpitt and Clapp oscillators, all with a fully integrated tank are reported. In this study, different MMIC/RFIC technologies such as SiGe HBT, InGaP-GaAs-HBT, PHEMT, MHEMT, and CMOS are represented and parameters such as phase-noise, output power, dc-power consumption, and tuning range are compared. All oscillators are designed for low phase noise. Low phase noise can be achieved by CMOS, PHEMT and MHEMT technologies although SiGe and InGaP-GaAs HBT based oscillators have demonstrated the lowest phase noise. Both fundamental and second harmonic VCOs are represented in the evaluation.

A 5-25 GHz high linearity, low-noise CMOS amplifier

A very wide-band amplifier has been designed in a 90 nm CMOS process, utilizing a common source topology with shunt resistor-inductor feedback. Both input and output return loss was better than 10 dB from 6 to 23 GHz for a one-stage amplifier and from 5 to 26 GHz for a two-stage version. The gain varied from 6 to 9 dB for the one-stage amplifier and from 12 to 16 dB for the two-stage amplifier over that frequency range. The noise figure is below 7 dB over 5-26 GHz for both amplifiers. At 20 GHz the input IP3 of the one- and two-stage amplifiers were 14 dBm and 6 dBm, respectively

A 20 GHz sub-1V low noise amplifier and a resistive mixer in 90 nm CMOS technology

A 20 GHz sub-1 V low noise amplifier and a resistive mixer are designed and fabricated in 90 nm CMOS technology. The LNA achieves a good linearity along with a moderate gain and noise figure. For instance, at 0.9 V supply voltage, 8.8 dB of gain and 5.2 dB of noise figure, as well as 7.0 dBm of IIP3 are obtained. This LNA can work properly even at a supply voltage as low as 0.66 V. It achieves 8.0 dB of gain, 5.3 dB of noise figure, and 3.8 dBm of III3. The DC consumption is 16.8 mW and 11 mW for a supply voltage of 0.9 V and 0.66 V, respectively. This is the first report of a high frequency CMOS LNA operating at such low supply voltage and low DC power dissipation. Moreover, a 20 GHz resistive passive mixer is presented, exhibiting a high IIP3 of 19 dBm, a moderate conversion loss of 7.6 dB, and a low noise figure of 4.35 dB. It consumes no DC power. Thus, these two circuits are suitable to be applied in a high frequency CMOS front-end operating with sub-1 V supply.

A 23 GHz active mixer with integrated diode linearizer in SiGe BiCMOS technology

Active mixers operating at 23 GHz are designed and fabricated in SiGe technology. An integrated diode linearizer is used to improve the linearity of the mixer. Measurement and simulation show excellent agreement. Typically, 10 dB double-sideband noise figure, 10 dBm IIP3 and 2 dB conversion gain are measured, featuring low noise and high linearity in a same design.