Laurent Rubaldo

230-GHz self-aligned SiGeC HBT for optical and millimeter-wave applications

This paper describes a 230-GHz self-aligned SiGeC heterojunction bipolar transistor developed for a 90-nm BiCMOS technology. The technical choices such as the selective epitaxial growth of the base and the use of an arsenic-doped monocrystalline emitter are presented and discussed with respect to BiCMOS performance objectives and integration constraints. DC and high-frequency device performances at room and cryogenic temperatures are given. HICUM model agreement with the measurements is also discussed. Finally, building blocks with state-of-the-art performances for a CMOS compatible technology are presented: A ring oscillator with a minimum stage delay of 4.4 ps and a 40-GHz low-noise amplifier with a noise figure of 3.9 dB and an associated gain of 9.2 dB were fabricated.

230 GHz self-aligned SiGeC HBT for 90 nm BiCMOS technology

This paper describes a 230 GHz self-aligned SiGeC HBT featuring a selective epitaxial base and an arsenic-doped monocrystalline emitter. These technical choices are presented and discussed with respect to BiCMOS performance objectives and integration constraints.

300 GHz f/sub max/ self-aligned SiGeC HBT optimized towards CMOS compatiblity

This paper summarizes the work carried out to improve performances of a SiGeC HBT featuring a selective epitaxial base and an arsenic-doped monocrystalline emitter. A 300 GHz f/sub max/ is reported for a transistor sustaining high thermal budget.

A self-aligned vertical HBT for thin SOI SiGeC BiCMOS

We demonstrate a 4-mask HBT module, which enables the integration of three high performance self-aligned SiGeC HBTs into a 0.13/spl mu/m SOI CMOS technology. Static and dynamic transistor characteristics are described and compared with simulation results and bulk device performances.

250-GHz self-aligned Si/SiGeC HBT featuring an all-implanted collector

This paper presents investigations led to simplify the collector module of SiGeC HBTs in order to reduce technology cost. Outcome of this work is an HBT featuring an all-implanted collector with record fT and fmax (>250 GHz)

Deep trench isolation effect on self-heating and RF performances of SiGeC HBTs

This paper focuses on the effect of deep trench isolation (DTI) on self-heating and electrical performances of state-of-the-art SiGeC heterojunction bipolar transistors (HBTs). The influence of DTI on the heat dissipation and on the thermal resistance of HBTs is studied both with electrical measurements and simulations. The results show that the DTI has a significant influence on heat dissipation and on the thermal resistance values but only little impact on RF performances.

Tensile strain in arsenic heavily-doped Si

In this paper we highlight the existence of tensile stress in heavily arsenic-doped epitaxial silicon (Si:As) prepared by low pressure chemical vapor deposition. Despite the large size of As atoms compared to Si ones, we demonstrate with x-ray diffraction and convergent electron beam diffraction that the heavily doped epitaxial layers show a tetragonal lattice with a reduced out of plane parameter. Using positron annihilation spectroscopy, we highlight the formation of arsenic-vacancies defects during the growth. We show that the tensile strain is related to this type of defects involving inactive As atoms and not to the As active concentration.

Development of a self-aligned pnp HBT for a complementary thin-SOI SiGeC BiCMOS technology

This paper describes the development of a thin-SOI pnp SiGeC HBT using a self-aligned selective epitaxy emitter/base architecture. Static and dynamic device characteristics are presented, and first results from a full 130 nm thin-SOI complementary SiGeC BiCMOS technology are reported.

A 0.13μm thin SOI CMOS technology with low-cost SiGe:C HBTs and complementary high-voltage LDMOS

We demonstrate the integration, in 0.13μm thin SOI CMOS technology, of low-cost high-performance high-voltage LDMOS and HBT transistors. These specific devices are obtained, without affecting CMOS core process devices. Static and dynamic characteristics for both type of transistors are presented, showing state of the art devices suitable for RF/analog/digital system on chip integration.

Carbon effect on neutral base recombination in high-speed SiGeC HBTs

We have presented the performances and electrical behavior of high-speed SiGeC HBTs having enhanced NBR by carbon insertion in excess. The current gain is strongly reduced, so that BVCEO increases by 0.5 V, and the fT times BVCEO product shifts from 340 to 423 GHz.V, which offers new possibilities for HBTs optimization, notably by increasing collector doping. Thanks to the NBR, the current gain dependency with temperature above 300 K is reduced, which is interesting for applications such as power amplifiers. The current gain evolution with VBE is explained by trap saturation, which was confirmed in simulations by inserting a trap level in the base gap. The band gap dependency with carbon insertion is also demonstrated and was developed in the final paper