Michael Canonico

Si–Ge interdiffusion in strained Si/strained SiGe heterostructures and implications for enhanced mobility metal-oxide-semiconductor field-effect transistors

Si–Ge interdiffusivity in epitaxial strained Si∕Si1−yGey/strained Si/relaxed Si1−x0Gex0 heterostructures is extracted for Ge fractions between 0 and 0.56 over the temperature range of 770–920°C. Boltzmann-Matano analysis is applied to determine interdiffusivity from diffused Ge profiles in strained Si/relaxed Si1−x0Gex0 heterostructures [L. Boltzmann, Wiedemanns Ann. Phys. 53, 959 (1894) and C. Matano, Jpn. J. Phys. 8, 109 (1933)]. A model for the interdiffusivity suitable for use in the process simulator TSUPREM-4 is constructed. Si–Ge interdiffusivity increases by 2.2 times for every 10% increase in Ge fraction for interdiffusion in strained Si/relaxed Si1−x0Gex0 samples. Significantly enhanced Si–Ge interdiffusion is observed for Si1−yGey layers under biaxial compressive strain. Si–Ge interdiffusivity is found to increase by 4.4 times for every 0.42% increase in the magnitude of biaxial compressive strain in the Si1−yGey, which is equivalent to a decrease in the Ge percentage in the substrate by 10at.%...

Electron transport in Gate-All-Around uniaxial tensile strained-Si nanowire n-MOSFETs

The intrinsic performance and electron effective mobility of uniaxially strained-Si gate-all-around (GAA) NanoWire (NW) n-MOSFETs are investigated, for the first time. Suspended strained-Si NWs show very high stress (up to ~2.1 GPA) as confirmed by Raman, with no bending of the wires. GAA strained-Si NW n-MOSFETs exhibit excellent subthreshold swing, and current drive and transconductance enhancement of ~2X over unstrained Si control NW devices. The mobility enhancement of these devices over unstrained planar and GAA MOSFETs as well as their scalability to circular NWs with radius of ~4 nm are also demonstrated.

Embedded SiGe S/D PMOS on thin body SOI substrate with drive current enhancement

We report for the first time PMOS drive current enhancement with in-situ boron doped SiGe incorporation in recessed S/D regions for devices built on thin body SOI substrate. For P-channel PD-SOI devices with 450 A silicon on insulator and 38nm gate length, 35% linear drain current enhancement and 20% saturation drain current improvement have been achieved with this approach. Device integration and performance improvement are discussed below.

Strain dependence of Si–Ge interdiffusion in epitaxial Si∕Si1−yGey∕Si heterostructures on relaxed Si1−xGex substrates

The strain dependence of Si–Ge interdiffusion in epitaxial Si∕Si1−yGey∕Si heterostructures on relaxed Si1−xGex substrates has been studied using secondary ion mass spectrometry, Raman spectroscopy, and simulations. At 800 and 880 °C, significantly enhanced Si–Ge interdiffusion is observed in Si∕Si1−yGey∕Si heterostructures (y=0.56, 0.45, and 0.3) with Si1−yGey layers under compressive strain of −1%, compared to those under no strain. In contrast, tensile strain of 1% in Si0.70Ge0.30 layer has no observable effect on interdiffusion in Si∕Si0.70Ge0.30∕Si heterostructures. These results are relevant to the device and process design of high mobility dual channel and heterostructure-on-insulator metal oxide semiconductor field effect transistors.

Through Silicon Via stress characterization

In this paper, we will present Micro Raman stress data of Through Silicon Vias (TSV) with different shapes and sizes & spacing, and discuss design considerations.

Asymmetric strain in nanoscale patterned strained -Si/strained -Ge/strained-Si heterostructures on insulator

The engineering of asymmetric strain is demonstrated in nanoscale patterned strained-Si/strained-Ge/strained-Si heterostructure on insulator with body thickness of 15nm. Starting material has layers with symmetric in-plane strain, including biaxial strained Si (∼1.8%, tension) and biaxial strained Ge (∼1.8%, compression). Micro-Raman spectroscopy is utilized to characterize the stress in heterostructures patterned into 10-μm-long bars with widths ranging from 300to30nm. Raman measurements are consistent with the transformation from biaxial to uniaxial compressive strain in the Ge for 30-nm-wide bars, as predicated by simulations. Measurements also demonstrate enhanced asymmetric relaxation in the tensile strained Si cap as its thickness is increased.

Fabrication and Characterization of Suspended Uniaxial Tensile Strained-Si Nanowires for Gate-All-Around Nanowire n-MOSFETs

Suspended strained-Si nano-wires (NWs) were fabricated from a highly biaxially strained-Si substrate (with an initial stress of 2.16 GPa). Using e-beam lithography, ~25nm thick NWs with the widths in the range of 20 to 80 nm were fabricated and the stress was investigated by UV micro-Raman spectroscopy. Suspended NWs are strained to an average uniaxial tensile stress level of ~2.1 GPa which is almost independent of NW width, in the range studied in this work. Ultra-dense (25 NWs per micron) sub-20 nm suspended strained-Si NWs were fabricated using resolutionenhanced lithography to improve the Raman signal-to-noise ratio. A tensile in-plane stress level of 1.7GPa was measured for 18 nmwide NWs at 40 nm pitch. Gate-all-around n-MOSFETs were fabricated based on these strained-Si NWs. Electrical measurements on these MOSFETs demonstrate near ideal subthreshold behavior, very high on-to-off ratio and current drive and transconductance enhancement of ~2X over unstrained NWs.

Performance of super-critical strained-Si directly on insulator (SC-SSOI) CMOS based on high-performance PD-SOI technology

This paper describes the performance of multiple-V/sub T/, Triple-gate oxide SC-SSOI CMOS realized with Freescales high-performance silicon-on-insulator (HiPerMOS-SOI) and SOITECs advanced wafer-bonding technology. The thermal stability of wafer-bonded strained substrate, the beneficial impact of biaxial strain on gate-leakage and SC-SSOI enhanced SRAM bitcell operation are demonstrated for the first time. In-addition, the important scaling issues due to parasitic resistance and channel strain engineering are identified.

Strain-Enhanced CMOS Through Novel Process-Substrate Stress Hybridization of Super-Critically Thick Strained Silicon Directly on Insulator (SC-SSOI)

This paper describes a biaxial-uniaxial hybridized strained CMOS technology achieved through selective uniaxial relaxation of thick SSOI, dual-stress nitride capping layer, and embedded SiGe source/drain. Through novel strain engineering, nFET/pFET Idsat enhancements as high as 27%/36% have been achieved for sub-40nm devices at 1V with 30% reduction in gate leakage current, while introducing minimum process complexity. This work demonstrates the scalability of SC-SSOI and its advantages over pure biaxial and single uniaxial strained Si technologies

Super critical thickness SiGe-channel heterostructure p-type metal-oxide-semiconductor field-effect transistors using laser spike annealing

Strained Si/strained Si0.3Ge0.7/relaxed Si0.7Ge0.3 heterostructure p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) with high mobility and low leakage are demonstrated using laser spike annealing, despite a strained Si0.3Ge0.7 channel thickness that is two times the equilibrium critical thickness. Measured hole mobility is enhanced four times for Si0.3Ge0.7 channel MOSFETs relative to Si control devices, at an inversion charge density of 1013cm−2. For supercritical thickness strained SiGe channel films, the use of laser spike annealing allows source/drain annealing at significantly higher temperatures than is possible with rapid thermal annealing (e.g., 975 versus 800°C), while achieving superior leakage characteristics. For laser spike annealing temperatures above 1000°C, mobility is found to degrade due to partial relaxation and dislocation formation in the Si0.3Ge0.7 channel.