Li-Chen Yen

Electrical and reliability characteristics of polycrystalline silicon thin-film transistors with high-κ Eu2O3 gate dielectrics

In this study, we developed a high-performance low-temperature polycrystalline silicon thin-film transistor (LTPS-TFT) incorporating an ultra thin Eu2O3 gate dielectric. High-κ Eu2O3 LTPS-TFT annealed at 500 °C exhibits a low threshold voltage of 0.16 V, a high effective carrier mobility of 44 cm2/V-s, a small subthreshold swing of 142 mV/decade, and a high Ion/Ioff current ratio of 1.34 × 107. These significant improvements are attributed to the high gate-capacitance density due to the adequate quality of Eu2O3 gate dielectric with small interfacial layer of effective oxide thickness of 2.5 nm. Furthermore, the degradation mechanism of positive bias temperature instability was studied for a high-k Eu2O3 LTPS-TFT device.

Low-Temperature Polycrystalline-Silicon Tunneling Thin-Film Transistors With MILC

It is known that metal-induced lateral crystallization (MILC) thin-film transistors (TFTs) exhibit higher on-state current, steeper subthreshold slope, and lower minimum leakage than solid-phase-crystallization TFTs. In this letter, we propose a tunneling TFT (T-TFT) fabricated by MILC method for the first time. The MILC T-TFTs demonstrate a lower subthreshold swing, ~ 232 mV/decade, than the other T-TFTs and a high ON/OFF ratio at VDS=1 V without any hydrogen-related plasma treatment. These improvements can be due to the reduction of defects at grain boundaries and the channel direction parallel to grains. The polycrystalline silicon T-TFTs fabricated in this letter show a great promise for low standby power circuits, drivers of active-matrix liquid crystal displays, and 3-D integrated circuits applications in the future.

Improvement in pH Sensitivity of Low-Temperature Polycrystalline-Silicon Thin-Film Transistor Sensors Using H2 Sintering

In this article, we report an improvement in the pH sensitivity of low-temperature polycrystalline-silicon (poly-Si) thin-film transistor (TFT) sensors using an H2 sintering process. The low-temperature polycrystalline-silicon (LTPS) TFT sensor with H2 sintering exhibited a high sensitivity than that without H2 sintering. This result may be due to the resulting increase in the number of Si–OH2+ and Si–O− bonds due to the incorporation of H in the gate oxide to reduce the dangling silicon bonds and hence create the surface active sites and the resulting increase in the number of chemical reactions at these surface active sites. Moreover, the LTPS TFT sensor device not only offers low cost and a simple fabrication processes, but the technique also can be extended to integrate the sensor into other systems.

Effect of Sensing Film Thickness on Sensing Characteristics of Dual-Gate Poly-Si Ion-Sensitive Field-Effect-Transistors

We investigate the effect of sensing film thickness on the sensing characteristics of dual-gate (DG) poly-Si ion-sensitive field-effect transistors (ISFETs). The pH sensitivity (from 37.57 to 9.32 mV/pH) of the DG poly-Si ISFET device degrades with the increase in the sensing film thickness (from 20 to 120 nm), whereas hysteresis voltage (from 6.7 to 1.12 mV for a neutral to acid to alkaline to neural loop) and drift rate (from 13.47 to <;3 mV/h at pH 7) improve accordingly. An improved hysteresis and drift phenomena are attributed to the reduction in top-gate capacitance of the sensing membrane, causing a smaller capacitive-coupling ratio (top-gate capacitance of sensing membrane to bottom-gate capacitance of tetraethylorthosilicate oxide).

Symmetric Vertical-Channel Nickel-Salicided Poly-Si Thin-Film Transistors With Self-Aligned Oxide Overetching Structures

This paper reports the impacts of NH3 plasma treatment time, oxide overetching depth, and gate oxide thickness on symmetric vertical-channel Ni-salicided poly-Si thin-film transistors (VSA-TFTs) for the first time. off-state currents may be improved by increasing the oxide overetching depth. The on/ off current ratio may be also improved by increasing the oxide overetching depth. The NH3 plasma optimum treatment time of VSA-TFTs is significantly shorter than that of conventional top-gate horizontal-channel TFTs. The performance of VSA-TFTs is degraded by NH3 plasma treatment for too long a time. VSA-TFTs with 15-nm gate oxide thickness display better subthreshold swing (<; 150 mV/dec) than VSA-TFTs with 30-nm gate oxide thickness. off-state currents can be improved by increasing Lmask, even when the oxide overetching depth and the gate oxide thickness are changed.

Reliability Analysis of Symmetric Vertical-Channel Nickel-Salicided Poly-Si Thin-Film Transistors

In this paper, a reliability analysis of symmetric Vertical-channel Ni-SAlicided poly-Si thin-film transistors (VSA-TFTs) is performed for the first time. First, we compare the drain-induced barrier-lowering effect (DIBL) of VSA-TFTs. The VSA-TFTs with thinner gate oxide thickness, an offset structure, and a longer floating n+ region have better immunity to DIBL. Second, VSA-TFTs with a longer floating n+ region also have better immunity under hot-carrier (HC) stress and self-heating (SH) stress. However, VSA-TFTs with a shorter floating n+ region also have better immunity to positive gate bias (PGB) stress. Consequently, in order to optimize reliability characteristics, including SH stress, HC stress, and PGB stress, it is necessary to modulate the length of the floating n+ region. Third, the PGB stress, rather than SH stress or HC stress, becomes a major issue for VSA-TFTs under the stress bias below 4 V. In other words, PGB stress will dominate the degradation behaviors when the stress bias is not high enough to achieve SH stress and HC stress. Finally, the worst degradation condition of VSA-TFTs under HC stress, similar to that of most TFT devices, occurs when the stress of VG is less than half of VD.

Structural and Electrical Properties of High-k HoTiO3 Gate Dielectrics

To suppress the direct tunneling and maintain the gate capacitance, a SiO2 film has to be replaced by a highk gate dielectric with a large film thickness. Thin rareearth (RE) oxide films, such as La2O3, Pr2O3, Sm2O3, Ho2O3, and Er2O3 [1-5], are extremely promising high-k gate insulators in advanced microelectronic devices because their moderately high-k values as well as high conduction band offsets with Si. However, La2O3 film is hygroscopic forming hydroxide, which generates charges in the gate oxide and causes a large flat-band voltage shift [6]. The TiO2 combined with RE metal oxide films has attracted a lot of attention as a method to achieve a high-k dielectric material with excellent electrical properties [7]. A ~16 nm HoTiO3 film was deposited on the Si substrate through cosputtering Ho and Ti from a holmium target and titanium target in diluted O2 ambient. Samples were then annealed at different temperatures in O2 gas for 30 s by rapid thermal annealing (RTA) to form a HoTiO3 compound structure. A 1000 A TiN film was deposited on the HoTiO3 using sputtering to serve as the gate electrode. After annealing performed at 700°C, the HoTiO3 (112) and (311) reflection peaks were observed in the XRD patterns, as shown in Fig. 1. Moreover, (004) reflection peak is found but less intensity than for both (112) and (311) peaks. It was found that the (112) peak becomes stronger at higher annealing temperature of 800°C. Fig. 2 shows the Ho 4d, Ti 2p, and O 1s XPS spectra for the HoTiO3 film annealed at various temperatures. The Ho 4d peak at 163.2 eV of the HoTiO3 film moved toward higher binding energy compared to the Ho2O3 film (161.8 eV) [8]. At an annealing temperature of 800 °C, the Ho 4d peak at 163.2 eV corresponding to HoTiO3 bonds is observed in the XPS spectra. For the as-deposited film, suggesting a poor TiO2 structure incorporating Ti in the form of TiO2 or TiOH, which probably formed in the surface region of the sample during its exposure to air [9]. The shift in Ti 2p splitting location to higher binding energy increased upon increasing the RTA temperature, probably as a result of the existence of Ho–O–Ti bonds. In the three sets of spectra, the O 1s peaks at 529.8, 530.8, and 532.1 eV represent the Ho–O–Si, Ho–O–Ti, and Ho–O [8] bonds, respectively. The O 1s peak intensity corresponding to Ho-silicate and HoTiO3 is rather constant up to 700 °C but suddenly increases at 800 °C, whereas the O 1s peak intensity corresponding to Ho2O3 decreases with increasing the RTA temperature. This finding indicates that the formation of the low-k interfacial layer. The C-V curves of the HoTiO3 MOS devices after RTA treatments are given in Fig. 3 (a). The sample without RTA treatment exhibited a high and negative flatband voltage shift, suggesting a high oxide charge density due to a high number of crystal defects in the film. The negative flatband voltage of the HoTiO3 film decreased upon increasing the RTA temperature, whereas the capacitance value increased upon increasing the RTA temperature. Figure 3 (b) shows the J-V curves of the HoTiO3 MOS devices after RTA treatments. With increased RTA temperature (except 800 °C), the reduction in leakage current density was observed, possibly indicative of the formation of a well-crystallized HoTiO3 structure and a small interfacial trap and oxide charge in the film. Fig. 4 depicts the density of interface state and hysteresis voltage of HoTiO3 MOS devices as a function of RTA temperature. The HoTiO3 MOS device annealed at 800 °C exhibited a lower Dit value compared to the other annealing temperature. The HoTiO3 film annealed at 800 °C showed a low hysteresis voltage at the flatband region, suggesting a low density of interfacial trap and/or mobile charge in the oxide. References [1] W. He, S. Schuetz, R. Solanki, J. Belot, and J. McAndrew, Electrochemical and Solid-State Lett. 7, G131 (2004). [2] A. U. Mane, Ch. Wenger, T. Schroeder, P. Zaumseil, G. Lippert, G. Weidner, and H. J. Mussig, J. Electrochemical Soc. 152, C399 (2005). [3] T. M. Pan and C. C. Huang, Electrochemical and Solid-State Lett. 11, G62 (2008). [4] T. Wiktorczyk, Thin Solid Films 405, 238 (2002). [5] T. M. Pan, C. L. Chen, W. W. Yeh, and S. J. Hou, Applied Phys. Lett. 89, 222912 (2006). [6] A. R. Gonzales-Elipe, J. P. Espinos, A. Fernandez, and G. Munuera, Appl. Surf. Sci. 45, 103 (1990). [7] R. B. van Dover, Appl. Phys. Lett. 74, 3041(1999). [8] S. Jeon and H. Hwang, Appl. Phys. Lett., 81, 4856 (2002). [9] J. F. Moulder, W. F. Stickle, P. E. Sobol, and K. D. Bomben, Handbook of X-Ray Photoelectron Spectroscopy: A Reference Book of Standard Spectra for Identification and Interpretation of XPS Data (Physical Electronics. Chanhassen, Mn., 1995).

Enhanced Subthreshold Slope and On-state Current in Tunneling Thin-Film-Transistors Using Metal Induced Lateral Crystallization

In this study, we propose a tunneling TFT fabricated by MILC method for the first time. The MILC tunneling TFTs demonstrate a lower subthreshold swing, ~232 mV/dec, than the other tunneling TFTs (T-TFTs) and a high on/off ratio > 10 6 at VDS=1V without any hydrogen related plasma treatment.

High-κ Eu 2 O 3 and Y 2 O 3 Poly-Si Thin-Film Transistor Nonvolatile Memory Devices

In this paper, we have successfully fabricated low-temperature polycrystalline silicon thin-film transistor (LTPS-TFT) nonvolatile memory devices employing high-κ Eu₂O₃ and Y₂O₃ films as the charge trapping layer. The LTPS-TFT memory device uses band-to-band tunneling-induced hot hole injection and gate Fowler-Nordheim injection as the program and erase methods, respectively. Compared with the Y₂O₃ film, the LTPS-TFT memory device using an Eu₂O₃ charge-trapping layer exhibited a lower subthreshold swing and a larger memory window, a smaller charge loss, and a better endurance performance, presumably because of the higher charge-trapping efficiency of the Eu₂O₃ film.

High-

In this paper, we have successfully fabricated low-temperature polycrystalline silicon thin-film transistor (LTPS-TFT) nonvolatile memory devices employing high-κ Eu₂O₃ and Y₂O₃ films as the charge trapping layer. The LTPS-TFT memory device uses band-to-band tunneling-induced hot hole injection and gate Fowler-Nordheim injection as the program and erase methods, respectively. Compared with the Y₂O₃ film, the LTPS-TFT memory device using an Eu₂O₃ charge-trapping layer exhibited a lower subthreshold swing and a larger memory window, a smaller charge loss, and a better endurance performance, presumably because of the higher charge-trapping efficiency of the Eu₂O₃ film.