Po-Yi Kuo

The Impact of Deep Ni Salicidation and

In this letter, 50-nm gate-length nano-silicon-on-insulator FinFETs with deep Ni salicidation and NH3 plasma treatment are fabricated. It is found that device performances, including subthreshold slope (SS) drain-induced barrier lowering (DIBL) and off-state leakage current, can be greatly improved by using deep Ni salicidation process compared to no Ni salicidation process. The deep Ni-salicided devices effectively suppress the floating-body effect and parasitic bipolar junction transistor action. In addition, the effect of NH3 plasma on the deep Ni-salicided devices is discussed. Experimental results reveal that the devices under a new state-of-the-art NH3 plasma process can achieve better performance such as an SS of 66 mV/dec and a DIBL of 0.03 V

hboxNH_3

We have successfully fabricated novel sub-10-nm gate-all-around Si nanowire (NW) poly-Si TFTs with raised source/drain structure (GAA RSDNW-TFTs). The Si NW dimension is about 7×12 nm. A superior smooth elliptical shape is obtained, for the first time, in the category of poly-Si NW TFTs through the use of a novel fabrication process requiring no advanced lithographic tools. The GAA RSDNW-TFTs exhibit low supply gate voltage (3 V), steep subthreshold swing ~99 mV/dec, and high ION/IOFF >; 107 (VD = 1 V) without hydrogen-related plasma treatments. Furthermore, the DIBL of GAA RSDNW-TFTs is well controlled. These improvements can be attributed to the 3-D gate controllability, raised S/D structure, and sub-10-nm Si NW channel. These novel GAA RSDNW-TFTs are, thus, quite suitable for system-on-panel and 3-D IC applications.

Plasma Treatment on Nano-SOI FinFETs

The gate-all-around sidewall-damascened sub10-nm in situ n+-doped poly-Si nanowires channels junctionless FETs (GAA SWDNW-JLFETs) with one NW of sub-50-nm2 cross-sectional area have been successfully fabricated and demonstrated in the category of poly-Si NWs JL transistors for the first time. Some key properties are explored: 1) novel SWDNW processes; 2) dependence of threshold voltage (VTii) and subthreshold swing (S.S.) on dimension of in situ n+-doped poly-Si NWs in GAA SWDNW-JLFETs; and 3) thermal stability of main electrical characteristics under high operating temperature. The high-performance GAA SWDNW-JLFETs show good electrical characteristics: 1) steep S.S. ~ 75 mV/decade; 2) low gate supply voltage (VG ) = 1.5 V; 3) high ON/OFF currents ratio (ION/IOFF) ~ 8 × 107 and significantly high-thermal stability without implantation processes and hydrogen-related plasma treatments for future 3-D integrated circuits, system-on-panel, and system-on-chip applications.

Novel Sub-10-nm Gate-All-Around Si Nanowire Channel Poly-Si TFTs With Raised Source/Drain

In this letter, we developed a new self-aligned Schottky barrier source and ohmic body contact (SSOB) method that can effectively suppress the floating-body effect in poly-Si thin-film transistors (TFTs). Experimental results show that the SSOB-TFTs give higher output resistance, less threshold voltage variation, improved subthreshold characteristics, and larger breakdown voltage compared with conventional TFTs. The characteristics of the SSOB-TFTs are suitable for high-performance driving TFTs with a high output resistance and large breakdown voltage.

High-Performance GAA Sidewall-Damascened Sub-10-nm In Situ n + -Doped Poly-Si NWs Channels Junctionless FETs

It is known that metal-induced lateral crystallization (MILC) thin-film transistors (TFTs) exhibit higher on-state current, steeper subthreshold slope, and lower minimum leakage than solid-phase-crystallization TFTs. In this letter, we propose a tunneling TFT (T-TFT) fabricated by MILC method for the first time. The MILC T-TFTs demonstrate a lower subthreshold swing, ~ 232 mV/decade, than the other T-TFTs and a high ON/OFF ratio at VDS=1 V without any hydrogen-related plasma treatment. These improvements can be due to the reduction of defects at grain boundaries and the channel direction parallel to grains. The polycrystalline silicon T-TFTs fabricated in this letter show a great promise for low standby power circuits, drivers of active-matrix liquid crystal displays, and 3-D integrated circuits applications in the future.

Suppression of the floating-body effect in poly-Si thin-film transistors with self-aligned Schottky barrier source and ohmic body contact structure

In this paper, we have successfully developed and fabricated self-aligned Si/Ge T-gate poly-Si thin-film transistors (Si/Ge T-gate TFTs) with a thick gate oxide at the gate edges near the source and drain for the first time. The Si/Ge T-gate was formed by selective wet etching of Ge gate layer. The thick gate oxide layer at the gate edges and passivation oxide layer were deposited simultaneously in passivation process. The thick gate oxide at the gate edges effectively reduces the drain vertical and lateral electric fields without additional mask, lightly doped drain, spacer, or subgate bias. The Si/Ge T-gate TFTs not only reduce the off-state leakage current but also maintain a high on-state current. Experimental results show that the Si/Ge T-gate TFTs have low off-state leakage currents, improved on/off current ratio, and more saturated output characteristics compared with conventional TFTs

Low-Temperature Polycrystalline-Silicon Tunneling Thin-Film Transistors With MILC

In this paper, silicon-oxide-nitride-oxide-semiconductor (SONOS) devices with embedded silicon nanocrystals (Si-NCs) in silicon nitride using in situ method with multilevel and 2-b/cell operation have been successfully demonstrated. The proposed in situ Si-NC deposition method exhibits the advantages of low cost, simplicity, and compatibility with modern IC processes. SONOS memories with embedded Si-NCs exhibit a significantly improved performance with a large memory window (> 5.5 V), low operating voltage (P/E voltage: V_g = 6 V, V_d = 7 V and V_g = -7 V, V_d = 10 V, respectively), greater tolerable gate and drain disturbance (V_t shift <; 0.2 V), negligible second-bit effect, high P/E speed (after programming time = 10 μs with a 2-V shift of V_t under V_g = V_d = 6 V operation), good retention time (> 10⁸ s for 13% charge loss), and excellent endurance performance (after 10⁴ P/E cycles with a memory window of 3 V).

Characteristics of Self-Aligned Si/Ge T-Gate Poly-Si Thin-Film Transistors With High on / off Current Ratio

In this letter, for the first time, one-time-programmable (OTP) memory fabricated on the low-temperature poly-Si p-channel thin-film transistor (TFT) with metal-induced lateral-crystallization channel layer and high-kappa dielectrics is demonstrated. The state of this OTP memory can be identified by the scheme of gate-induced drain leakage current measurement. The OTP-TFT memory has good electrical characteristics in terms of low threshold voltage Vth ~ -0.78 V, excellent subthreshold swing ~ 105 mV/dec, low operation voltage, faster programming speeds, and excellent reliability characteristics.

Characteristics of SONOS-Type Flash Memory With In Situ Embedded Silicon Nanocrystals

We have successfully developed and fabricated a poly-Si thin-film transistor (poly-Si TFT) nonvolatile memory using Ge nanocrystals (Ge-NCs) as a charge trapping layer. Process compatibility and memory operation of the device were investigated. The Ge-NC trapping layer was directly deposited by low-pressure chemical vapor deposition at 370degC. Results show that the new poly-Si TFT nonvolatile Ge-NC memory has good programming/erasing efficiency, long charge retention time, and good endurance characteristics. These results show that poly-Si TFT nonvolatile Ge-NC memory is the promising nonvolatile memory candidate for system-on-panel application in the future.

MILC-TFT With High-

In this work, we have successfully demonstrated SONOS memories with embedded Si-NCs in silicon nitride by in-situ deposition method. The self-assembly silicon nanocrystals were in-situ deposited within the Si3N4 storage layer by dissociation of dichlorosilane (SiH2Cl2) gas to a high density of 9 times 1011 cm-2. This new structure exhibits larger memory windows for up to 6 V, better program/erase characteristics, and excellent data retention properties as compared to control device. In addition, this novel process is simple, low cost, and compatible to the standard complementary metal-oxide-semiconductor (CMOS) processes. This technology seems to be very promising for the advanced flash memory devices.