Zhao Zhenyu

The Effect of Re-Convergence on SER Estimation in Combinational Circuits

Detailed analysis is presented on the effect of re-convergence on SER estimation in combinational circuits. The results show that the ignoring of re-convergence by previous independent pulse methods introduces significant errors in SER results. Furthermore, independent pulse methods miscalculate the SET sensitive nodes, leading to improper hardening strategy.

Modeling and analysis of single-event transients in charge pumps

It has been shown that charge pumps (CPs) dominate single-event transient (SET) responses of phase-locked loops (PLLs). Using a pulse to represent a single event hit on CPs, the SET analysis model is established and the characteristics of SET generation and propagation in PLLs are revealed. An analysis of single event transients in PLLs demonstrates that the settling time of the voltage-controlled oscillators (VCOs) control voltage after a single event strike is strongly dependent on the peak control voltage deviation, the SET pulse width, and the settling time constant. And the peak control voltage disturbance decreases with the SET strength or the filter resistance. Furthermore, the analysis in the proposed PLL model is confirmed by simulation results using MATLAB and HSPICE, respectively.

A radiation-hardened-by-design technique for improving single-event transient tolerance of charge pumps in PLLs

A radiation-hardened-by-design (RHBD) technique for phase-locked loops (PLLs) has been developed for single-event transient (SET) mitigation. By presenting a novel SET-resistant complementary current limiter (CCL) and implementing it between the charge pump (CP) and the loop filter (LPF), the PLLs single-event susceptibility is significantly decreased in the presence of SETs in CPs, whereas it has little impact on the loop parameters in the absence of SETs in CPs. Transistor-level simulation results show that the CCL circuit can significantly reduce the voltage perturbation on the input of the voltage-controlled oscillator (VCO) by up to 93.1 % and reduce the recovery time of the PLL by up to 79.0%. Moreover, the CCL circuit can also accelerate the PLL recovery procedure from loss of lock due to phase or frequency shift, as well as a single-event strike.

A low-noise PLL design achieved by optimizing the loop bandwidth

This paper describes a low-noise phase-locked loop (PLL) design method to achieve minimum jitter. Based on the phase noise properties extracted from the transistor, and the low-pass or high-pass transfer characteristics of different noise sources to the output, an optimal loop bandwidth design method, derived from a continuous-time PLL model, further improves the jitter characteristics of the PLL. The described method not only finds the optimal loop-bandwidth to minimize the overall PLL jitter, but also achieves optimal loop-bandwidth by changing the value of the resistor or charge pump current. In addition, a phase-domain behavioral model in ADS is presented for accurately predicting improved jitter performance of a PLL at system level. A prototype PLL designed in a 0.18μm CMOS technology is used to investigate the accuracy of the theoretical predictions. The simulation shows significant performance improvement by using the proposed method. The simulated RMS and peak-to-peak jitter of the PLL at the optimal loop-bandwidth are 10.262 ps and 46.851 ps, respectively.

A single-event transient hardened phase-locked loop in 0.18 µm CMOS process

By implementing a novel complementary current limiter (CCL), a phase-locked loop (PLL) has been developed for improved single-event transient (SET) tolerance in 0.18 µm CMOS process. Simulation results show that the CCL circuit can significantly reduce the voltage perturbation on the input of the voltage-controlled oscillator (VCO) by up to 92.8%, and reduce the recovery time of the PLL by up to 76.4% in the presence of SETs in the charge pump (CP). And it can also improve the error pulses and phase displacement of the output clock greatly. Moreover, the CCL circuit can be readily applied to other PLL topologies1.

Verilog-A based implementation for coupled model of single event transients in look-up table technique

A Verilog-A based implementation of voltage coupled model is developed for Single-Event Transients (SETs) in microelectronic circuits. By implementing a look-up table in Verilog-A, the SET current source performs well and consents with the results from Technology CAD (TCAD) based mix-mode simulation. Simulation results from Synopsys Hspice 2008 indicates that the method proposed in this paper correctly reveals the current “tail” which reflects the equilibrium course of charge collection. Moreover, the Verilog-A based method speeds up the simulation by over 18,000 times than the mix-mode simulation and is also faster than the piecewise linear source (PWL). Furthermore, this Verilog-A based LUT method cooperates with the design flow well and can be easily applied to various applications with wide supports of industrial EDA tools1.

Analyze of current components in NMOS single event transient

3D mixed-mode simulation is used to research current components of SET current pulse in inverter chain, compared with that in a single NMOS. It is found that parasitic bipolar conduction current is the major component in SET current of single NMOS, but not in deep-submicron CMOS circuit. The paper provides a detailed discussion of source current in SET and it shows that negative and positive components of source current are related to bipolar amplification and diffusion of carriers respectively.