Li Wei Chu

ESD Protection Design for 60-GHz LNA With Inductor-Triggered SCR in 65-nm CMOS Process

To effectively protect the radio-frequency (RF) circuits in nanoscale CMOS technology from electrostatic discharge (ESD) damages, the silicon-controlled rectifier (SCR) devices have been used as main on-chip ESD protection devices due to their high ESD robustness and low parasitic capacitance. In this paper, an SCR device assisted with an inductor is proposed to improve the turn-on efficiency for ESD protection. Besides, the inductor can be also designed to resonate with the parasitic capacitance of the SCR device at the selected frequency band for RF performance fine tuning. Experimental results of the ESD protection design with inductor-triggered SCR in a nanoscale CMOS process have been successfully verified at 60-GHz frequency. The ESD protection design with inductor-triggered SCR has been implemented in cell configuration with compact size, which can be directly used in the RF receiver circuits. To verify the RF characteristics and ESD robustness in the RF receiver, the inductor-triggered SCR has been applied to a 60-GHz low-noise amplifier (LNA). Verified in a silicon chip, the 60-GHz LNA with the inductor-triggered SCR can achieve good RF performances and high ESD robustness.

Self-matched ESD cell in CMOS technology for 60-GHz broadband RF applications

A self-matched ESD cell library has been implemented in a commercial sub-100nm CMOS process for 60-GHz broadband RF applications. This ESD cell library has reached the 50-Ω input/output matching to reduce the design complexity for RF circuit designer and to provide suitable electrostatic discharge (ESD) protection. Experimental results of this ESD cell library have successfully verified the ESD robustness and the RF characteristics in the 60-GHz frequency band. This self-matched ESD cell library is easily to be used for ESD protection design in the 60-GHz broadband RF applications.

Design and implementation of configurable ESD protection cell for 60-GHz RF circuits in a 65-nm CMOS process

The configurable electrostatic discharge (ESD) protection cells have been implemented in a commercial 65-nm CMOS process for 60-GHz RF applications. The distributed ESD protection scheme was modified to be used in this work. With the consideration of parasitic capacitance from I/O pad, the ESD protection cells have reached the 50-Ω input/output matching to reduce the design complexity for RF circuit designer and to provide suitable ESD protection. Experimental results of these ESD protection cells have successfully verified the ESD robustness and the RF characteristics in the 60-GHz frequency band. These ESD protection cells can easily be used for ESD protection design in the 60-GHz RF applications, and accelerate the design cycle.

Modified LC-tank ESD protection design for 60-GHz RF applications

Nanoscale CMOS technologies, which were sensitive to electrostatic discharge (ESD), have been widely used to implement radio-frequency (RF) integrated circuits. Against ESD damages, ESD protection design must be included in RF circuits. A novel modified LC-tank ESD protection design was presented in this work. Such ESD protection circuit had been designed for 60-GHz RF applications and verified in a 65-nm CMOS process. The modified LC-tank can lower the power loss and reduce the layout area under the required human-body-model (HBM) ESD robustness, as compared with the traditional designs. With the better performances, the modified LC-tank ESD protection design was very suitable for RF ESD protection.

ESD protection structure with inductor-triggered SCR for RF applications in 65-nm CMOS process

To protect radio-frequency (RF) integrated circuits from electrostatic discharge (ESD) damages, silicon-controlled rectifier (SCR) devices have been used as main on-chip ESD protection devices due to their high ESD robustness and low parasitic capacitance in nanoscale CMOS technologies. In this work, the SCR device assisted with an inductor to resonate at the selected frequency band for RF performance fine tune was proposed. Besides, the inductor can be also designed to improve the turn-on efficiency of the SCR device for ESD protection. Verified in a 65-nm CMOS process, the ESD protection design with the inductor-triggered SCR for 60-GHz RF applications can achieve good RF performances and high ESD robustness.

Improving ESD robustness of stacked diodes with embedded SCR for RF applications in 65-nm CMOS

To protect the radio-frequency (RF) integrated circuits from the electrostatic discharge (ESD) damage in nanoscale CMOS process, the ESD protection circuit must be carefully designed. In this work, stacked diodes with embedded silicon-controlled rectifier (SCR) to improve ESD robustness was proposed for RF applications. Experimental results in 65-nm CMOS process show that the proposed design can achieve low parasitic capacitance, low turn-on resistance, and high ESD robustness.

Robust ESD Protection Design for 40-Gb/s Transceiver in 65-nm CMOS Process

To protect a 40-Gb/s transceiver from electrostatic discharge (ESD) damages, a robust ESD protection design has been proposed and realized in a 65-nm CMOS process. In this paper, diodes are used for ESD protection and inductors are used for high-speed performance fine tuning. Experimental results of the test circuits have been successfully verified, including high-speed performances and ESD robustness. The proposed design has been further applied to a 40-Gb/s current-mode logic (CML) buffer. Verified in silicon chip, the 40-Gb/s CML buffer with the proposed design can achieve good high-speed performance and high ESD robustness.

Design of Compact ESD Protection Circuit for V-Band RF Applications in a 65-nm CMOS Technology

Nanoscale CMOS technologies have been widely used to implement radio-frequency (RF) integrated circuits. However, the thinner gate oxide and silicided drain/source in nanoscale CMOS technologies seriously degraded the electrostatic discharge (ESD) robustness of RF circuits. Against ESD damage, an on-chip ESD protection design must be included in the RF circuits. As the RF circuits operate in the higher frequency band, the parasitic effect from ESD protection circuit must be strictly limited. To provide the effective ESD protection for a 60-GHz low-noise amplifier with less RF performance degradation, two new ESD protection circuits were studied in a 65-nm CMOS process. Such compact ESD protection circuits have been successfully verified in silicon chip to achieve the 2-kV human-body-model ESD robustness with the low insertion loss in small layout area. With the better performances, the proposed ESD protection circuits were very suitable for V-band RF ESD protection.

Design of Dual-Band ESD Protection for 24-/60-GHz Millimeter-Wave Circuits

To effectively protect the millimeter-wave (MMW) circuits in nanoscale CMOS technology from electrostatic discharge (ESD) damages, a dual-band ESD protection cell for 24-/60-GHz ESD protection is presented in this paper. The proposed ESD protection cell consisted of a diode, a silicon-controlled rectifier, a PMOS, and two inductors. To verify the dual-band characteristics and ESD robustness, the proposed ESD protection circuit had been applied to a 24-/60-GHz low-noise amplifier (LNA). The measurement results showed over-2-kV human-body-model ESD robustness with little performance degradation on LNA. The proposed dual-band ESD protection cell was suitable for circuit designers for them to easily apply ESD protection in the dual-band MMW circuits.

Design of ESD protection for RF CMOS power amplifier with inductor in matching network

Due to the potential for mass production, CMOS technologies have been widely used to implement radio-frequency integrated circuits (RF ICs). Electrostatic discharge (ESD), which is one of the most important reliability issues in CMOS technologies, must be considered in RF ICs. In this work, an on-chip ESD protection design for RF power amplifier (PA) was presented. The ESD protection design consisted of an inductor in the matching network of PA. The PA with this ESD protection had been designed and fabricated in a 65-nm CMOS process. The ESD-protected PA can sustain over 4-kV human-body-mode (HBM) ESD stress, while the unprotected PA was degraded after 1-kV HBM ESD stress.