Ming-Hsiang Song

A Wideband Low Noise Amplifier With 4 kV HBM ESD Protection in 65 nm RF CMOS

This study presents a wideband low noise amplifier (LNA) including electrostatic discharge (ESD) protection circuits using 65 nm CMOS with a gate oxide thickness of only ~ 2 nm. By co-designing the ESD blocks with the core circuit, the LNA shows almost no performance degradation compared to the reference design without ESD. Under a power consumption of only 6.8 mW, the silicon results show that the LNA can achieve a peak power gain of 13.8 dB. Within the 3 dB bandwidth from 2.6 GHz to 6.6 GHz, the noise figure (NF) is in a range of 4.0 dB to 6.5 dB and the input reflection coefficient S 11 is below -13.0 dB. Using the miniaturized Shallow-Trench-Isolation (STI) diode of ~ 40 fF capacitance and a robust gate-driven power clamp configuration, the proposed LNA demonstrates an excellent 4 kV human body mode (HBM) ESD performance, which has the highest voltage/capacitance ratio ( ~ 100 V/fF) among the published results for RF LNA applications.

Gated and STI defined ESD diodes in advanced bulk FinFET technologies

In CMOS scaling roadmap, bulk FinFET is the mainstream technology for sub-20nm nodes. However, newly introduced process options in advanced bulk FinFET technologies can result in significant impacts on intrinsic ESD performance. In this work, two types of ESD protection diodes are studied and the corresponding TCAD simulations bring an in-depth understanding on the failure mechanism of these ESD diodes.

An ultra-low power K-band low-noise amplifier co-designed with ESD protection in 40-nm CMOS

This paper presents a K-band low noise amplifier (LNA) co-designed with ESD protection circuit in 40-nm CMOS technology. By treating ESD devices as a part of the input matching network, an ESD protected 24-GHz LNA is demonstrated with a NF of 3.2 dB under a power consumption of only 4.1 mW. The ESD protection network is composed of dual-diode and a gate-driven power clamp achieving an ESD level of 2.8 kV human body model (HBM). Owing to the co-design approach, the NF only degrades by 0.2 dB compared with the reference LNA without the ESD network. The ESD-LNA presents a power gain of 13.0 dB with the input and output return losses both greater than 10 dB. To the best of our knowledge, this is the first report on a 24-GHz ESD-protected LNA in 40-nm CMOS.

A 6.5kV ESD-protected low noise amplifier in 65-nm CMOS

A new ESD topology is proposed for RF low-noise amplifier (LNA). By using the modified silicon-controlled rectifier (MSCR) in conjunction with a P+/N-well diode clamp, a 5.8-GHz LNA with 6.5-kV ESD protection circuit is demonstrated by a 65-nm CMOS technology. Compared with the reference design, the new topology enhances the ESD level from 3.5 kV to 6.5 kV for human body model (HBM) while the noise figure (NF) is only 0.13 dB higher. Under a supply voltage of 1.2 V and drain current of 6.5 mA, the proposed ESD-protected LNA has a NF of 2.57 dB with an associated power gain of 16.7 dB. The input third-order intercept point (IIP3) is −11 dBm and the input and output return losses are below −15.9 dB and −20 dB, respectively.

An on-chip combo clamp for surge and universal ESD protection in bulk FinFET technology

A surge protection consisted of the ready-made ESD clamp transistors has been designed and characterized in FINFET technology. It can endure all the stresses from CDM, HBM and Surge events. Compared to a conventional 0.7V RC-based core ESD clamp, the proposed cell greatly boosts the Surge immunity from 4V to 19V.

A 60 V Tolerance Transceiver With ESD Protection for FlexRay-Based Communication Systems

In this paper, a 60 V tolerance transceiver with ESD (electrostatic discharge) protection is proposed for FlexRay-based communication systems. The FlexRay transceiver comprises three protective devices, including an over-voltage detector, high-voltage ESD devices, and high-voltage diodes. The over-voltage detector is in charge of detecting bus (BP and BM) status to distinguish whether any hazard has happened. If the over-voltage detector is activated, the FlexRay transceiver must be turned off for safety. The high-voltage ESD device uses a base-floating PNP serving as a bi-directional device. Besides, it can protect the FlexRay transceiver whenever it is short-circuited in positive or negative high voltages. Notably, the high-voltage diode will eliminate the negative leakage current when negative high voltage hazards appear in FlexRay channels. An experimental prototype is implemented using a 0.18 μm CMOS mixed-signal based generation II HV BCD process. The measurement results justify the functional correctness and 60 V tolerance of the proposed FlexRay transceiver design.

FinFET SCR structure optimization for high-speed serial links ESD protection

An optimized SCR structure was proposed for high turn-on speed and low parasitic capacitance in FinFET CMOS process. Experimental results indicate that the proposed SCR structure delivers the best known results among the literatures (140mA/fF). By adopting the structure, ESD protection design for multi Gb/s transceiver can be simply realized.

Novel dual direction PNP with self-bias ring structure

A novel voltage rating adjustable dual direction PNP ESD clamp with self-bias ring structure is proposed and demonstrated for better isolation performance in this work. In comparison to conventional structure, measurements exhibit that the latch-up (LU) immunity are enhanced by more than 2.5X, and the leakage current level is simultaneously suppressed by more than 20X.

Bias Temperature Stress (BTS) induced ESD device's leakage issue and Its preventing solutions in smart power technology

A leakage issue induced by Bias Temperature Stress (BTS) is found in a NPN-based ESD clamp. BTS (1.1*Vdd, 125C, 8hrs) can cause an accumulation of drifted ions at an/the STI interface which leads to increased leakage and eventual device failure. TCAD simulation and activation energy extraction model are used to explain the mechanism and two solutions are proposed.

An analog front-end circuit with dual-directional SCR ESD protection for UHF-band passive RFID tag

In this study, we demonstrate an analog front-end (AFE) circuit with ESD protection for a passive RFID tag at UHF-band (860∼960 MHz) in a 0.18-μm CMOS technology. A dual-directional silicon-controlled-rectifier (dual-SCR) structure is proposed for the ESD protection under the large-signal operation at the RFID input. With the well-designed dual-SCR, a large trigger voltage (VT) of ∼ 16.9 V is obtained. The parasitic capacitance of the ESD block is only ∼ 34 fF, which has virtually no impact on the core circuits at the frequency of interest. The measured ESD levels achieve 3.0-kV human-body-mode (HBM) and 200-V machine-mode (MM), respectively. The RF-DC rectifier in the RFID circuit can generate a stable power supply output about 1.2 V when the RF input power exceeds −7.5 dBm.