Liang-Teck Pang

Large-Scale SRAM Variability Characterization in 45 nm CMOS

Increased process variability presents a major challenge for future SRAM scaling. Fast and accurate validation of SRAM read stability and writeability margins is crucial for estimating yield in large SRAM arrays. Conventional SRAM read/write metrics are characterized through test structures that are able to provide limited hardware measurement data and cannot be used to investigate cell bit fails in functional SRAM arrays. This work presents a method for large-scale characterization of read stability and writeability in functional SRAM arrays using direct bit-line measurements. A test chip is implemented in a 45 nm CMOS process. Large-scale SRAM read/write metrics are measured and compared against conventional SRAM stability metrics. Results show excellent correlation to conventional SRAM read/write metrics as well as VMIN measurements near failure.

Measurement and Analysis of Variability in 45 nm Strained-Si CMOS Technology

A test-chip in a low-power 45 nm technology, featuring uniaxial strained-Si, has been built to study variability in CMOS circuits. Systematic layout-induced variation, die-to-die (D2D), wafer-to-wafer (W2W) and within-die (WID) variability has been measured over multiple wafers, analyzed and attributed to likely causes in the manufacturing process. Delay is characterized using an array of ring oscillators and transistor leakage current is measured with an on-chip ADC. The key results link systematic layout-dependent and die-to-die variability as being caused by gate patterning and material strain. In comparison to a previous 90 nm experiment, gate proximity now contributes less to frequency variability, causing a 2% change in overall performance, while strain has increased its contribution to about 5% of the overall performance.

Impact of Layout on 90nm CMOS Process Parameter Fluctuations

A test chip has been built to study the effects of layout on the delay and leakage of digital circuits in 90nm CMOS. The delay is characterized through the spread of ring oscillator frequencies and the transistor leakage is measured by using an on-chip ADC

Measurements and Analysis of Process Variability in 90 nm CMOS

A test chip has been built to study the effects of circuit layout on variability, and to characterize within-die (WID) and die-to-die (D2D) variability of delay and leakage current in 90 nm CMOS technology. Delay is obtained through the measurement of ring oscillator frequencies, and the transistor leakage current is measured by an on-chip analog-to-digital converter (ADC). It has been found that the transistor performance depends strongly on the polysilicon (poly-Si) gate density, and the spatial correlation depends on the gate orientation and the direction of poly-Si spacing. WID variation is small with three standard deviations over a mean (3sigma/mu) of around 3.5%, whereas D2D and systematic layout-induced variations are significant, with a 3sigma/mu D2D variation of ~15% and a maximum layout-induced frequency shift of 10%. Finally, a set of guidelines is proposed to help circuit designers mitigate the effects of process variations on CMOS performance.

Measurement and analysis of variability in 45nm strained-Si CMOS technology

A test-chip in a low-power 45 nm technology, featuring uniaxial strained Si, has been built to study variability in CMOS circuits. Systematic layout-induced variation, die-to-die (D2D), wafer-to-wafer (W2W) and within-die (WID) variability has been measured and analyzed. Delay is characterized using an array of ring-oscillators and transistor leakage current is measured with an on-chip ADC. Results show that systematic variations are small and layout-induced variation is dominated by strain effects.

Large-scale read/write margin measurement in 45nm CMOS SRAM arrays

Distributions of read and write noise margins in large CMOS SRAM arrays are investigated by directly measuring the bit-line current during bitline / wordline (write) or cell supply (read) voltage sweep in a 768 Kb 45 nm CMOS SRAM test-chip. Good correlation between write/read margin estimates through the bit-line measurements and the DC read SNM (RSNM) and IW measurements in small on-chip SRAM macros with wired-out storage nodes are demonstrated. Four common writeability metrics are correlated and compared. Array-level characterization of SRAM cell read stability and writeability allow fast and accurate characterization of high-density SRAM arrays is scalable for capturing up to 6 standard deviations of parameter variations.

FinFET SRAM with Enhanced Read / Write Margins

In this work, the impact of this pass-gate feedback (PGFB) technique on cell write-ability is examined, and gate workfunction (Phim) tuning for optimization of the trade-off with read margin is discussed. To further improve cell write-ability, the p-channel pull-up devices can also be operated in BG mode, with their back gates driven by a separate write word line. This pull-up write gating (PUWG) technique is effective for maintaining larger than 6 standard deviations yield down to 0.4V VDD without area penalty, making FinFET-based 6-T SRAM compelling for high-density memory applications

Measurements and analysis of process variability in 90nm CMOS

Process variability in deeply scaled CMOS has both random and systematic components, with a varying degree of spatial correlation. A test chip has been built to study the effects of circuit layout on variability of delay and power dissipation in 90nm CMOS. The delay is characterized through the spread of ring oscillator frequencies and the transistor leakage is measured by using an on-chip ADC

Technology Variability From a Design Perspective

Increased variability in semiconductor process technology and devices requires added margins in the design to guarantee the desired yield. Variability is characterized with respect to the distribution of its components, its spatial and temporal characteristics and its impact on specific circuit topologies. Approaches to variability characterization and modeling for digital logic and SRAM are analyzed in this paper. Transistor arrays and ring oscillator arrays are designed to isolate specific systematic and random variability components in the design. Distributions of SRAM design margins are measured by using padded-out cells and observing minimum array operating voltages. Correlations between various components of variability are essential for adding appropriate margins to the design.

Compensation of systematic variations through optimal biasing of SRAM wordlines

Increasing process variability is slowing SRAM scaling by reducing both read and write margins. Existing techniques to compensate for systematic variations optimize cell stability with excessive penalty to writeability. To maximize overall yield, a sensor circuit is presented that optimizes the read / write tradeoff in the presence of process, voltage, and temperature variations. Sensors implemented in a low-power 45 nm test chip adjust the wordline voltage to track changes in the optimal value within 30 mV over the entire range of operation.