Lianxi Liu

A Hybrid Threshold Self-compensation Rectifier for RF Energy Harvesting

This paper presents a novel highly efficient 5-stage RF rectifier in SMIC 65 nm standard CMOS process. To improve power conversion efficiency (PCE) and reduce the minimum input voltage, a hybrid threshold self-compensation approach is applied in this proposed RF rectifier, which combines the gate-bias threshold compensation with the body-effect compensation. The proposed circuit uses PMOSFET in all the stages except for the first stage to allow individual body-bias, which eliminates the need for triple-well technology. The presented RF rectifier exhibits a simulated maximum PCE of 30% at −16.7 dBm (20.25 μW) and produces 1.74V across 0.5MΩ load resistance. In the circumstances of 1MΩ load resistance, it outputs 1.5V DC voltage from a remarkably low input power level of −20.4 dBm (9 μW) RF input power with PCE of about 25%.

A 1.33µW 10-bit 200KS/s SAR ADC with a tri-level based capacitor switching procedure

A 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) using an energy-efficient tri-level based capacitor switching procedure is presented. The proposed switching procedure achieves 97.66% less switching energy when compared to the conventional method. The number of unit capacitors is reduced by a factor of 4 over that of conventional architecture as well. To make the power consumption of the comparator scale down with respect to the comparison rate, the fully dynamic comparator is used. Moreover, the dynamic logic circuit is implemented to further reduce the power of digital circuits. The ADC is implemented in a 0.18µm 1P6M CMOS technology. At 1.0-V power supply and 200KS/s, the ADC achieves an SNDR of 60.54dB and consumes 1.33µW, resulting in a figure-of-merit (FOM) of 7.7fJ/conversion-step. The ADC core occupies an active area of only 230i?400?m2.

A LOW OFFSET COMPARATOR FOR HIGH SPEED LOW POWER ADC

A novel low offset, high speed, low power comparator architecture is proposed in this paper. In order to achieve low offset, both offset cancellation and dynamic amplifier techniques are adopted. Active resistors are chosen to implement the static amplifier circuit to obtain reduction in equivalent input referred offset voltage as well as to increase the circuit speed. The comparator is designed in TSMC 0.18 μm CMOS process. Monte Carlo simulation shows that the comparator has the offset voltage as low as 0.3 mV at 1 sigma at 250 MHz while dissipates 342 μW from a 1.8 V supply.

A high accuracy CMOS subthreshold voltage reference with offset cancellation and thermal compensation

This paper presents a high accuracy CMOS subthreshold voltage reference without BJTs for the low-supply-voltage and low-power application. The low supply voltage and low power dissipation are achieved, by making MOSFETs work in the subthreshold region. Besides, the offset scaling down (OSD) technique is proposed for the first time to cancel out the reference voltage variation caused by the offset of the clamping OTA. In addition, the pseudo-series-diodes are used with the negative temperature coefficient (TC) impendence for the second-order thermal compensation. Finally, the proposed voltage reference circuit is implemented in a standard 0.13m CMOS process, while the active silicon area is about 0.150.24mm2. At the minimum supply voltage 0.6V, the measured results shows a TC of 12.8ppm/C in the range of 2585C, and total power consumption of 373 nW. The line regulation is 0.15mV/V in the supply voltage range of 0.61.8V, and the variation of the reference voltage (/) is 1.28% without trimming and 0.42% after trimming, respectively. The power supply rejection ratio (PSRR) without any filtering capacitor at 1000Hz is 51dB for 0.6V supply and 73.8dB for 1.8V supply, respectively.

An Active Voltage Doubling Rectifier with Unbalanced-Biased Comparators for Piezoelectric Energy Harvesters

For wearable health monitoring systems, a fundamental problem is the limited space for storing energy, which can be translated into a short operational life. In this paper, a highly efficient active voltage doubling rectifier with a wide input range for micro-piezoelectric energy harvesting systems is proposed. To obtain a higher output voltage, the Dickson charge pump topology is chosen in this design. By replacing the passive diodes with unbalanced-biased comparator-controlled active counterparts, the proposed rectifier minimizes the voltage losses along the conduction path and solves the reverse leakage problem caused by conventional comparator-controlled active diodes. To improve the rectifier input voltage sensitivity and decrease the minimum operational input voltage, two low power common-gate comparators are introduced in the proposed design. To keep the comparator from oscillating, a positive feedback loop formed by the capacitor C is added to it. Based on the SMIC 0.18-μm standard CMOS process, the proposed rectifier is simulated and implemented. The area of the whole chip is 0.91×0.97 ㎟, while the rectifier core occupies only 13% of this area. The measured results show that the proposed rectifier can operate properly with input amplitudes ranging from 0.2 to 1.0V and with frequencies ranging from 20 to 3000 Hz. The proposed rectifier can achieve a 92.5% power conversion efficiency (PCE) with input amplitudes equal to 0.6 V at 200 Hz. The voltage conversion efficiency (VCE) is around 93% for input amplitudes greater than 0.3 V and load resistances larger than 20kΩ.

A self-powered piezoelectric energy harvesting interface circuit with efficiency-enhanced P-SSHI rectifier

The key to self-powered technique is initiative to harvest energy from the surrounding environment. Harvesting energy from an ambient vibration source utilizing piezoelectrics emerged as a popular method. Efficient interface circuits become the main limitations of existing energy harvesting techniques. In this paper, an interface circuit for piezoelectric energy harvesting is presented. An active full bridge rectifier is adopted to improve the power efficiency by reducing the conduction loss on the rectifying path. A parallel synchronized switch harvesting on inductor (P-SSHI) technique is used to improve the power extraction capability from piezoelectric harvester, thereby trying to reach the theoretical maximum output power. An intermittent power management unit (IPMU) and an output capacitor-less low drop regulator (LDO) are also introduced. Active diodes (AD) instead of traditional passive ones are used to reduce the voltage loss over the rectifier, which results in a good power efficiency. The IPMU with hysteresis comparator ensures the interface circuit has a large transient output power by limiting the output voltage ranges from 2.2 to 2 V. The design is fabricated in a SMIC 0.18 μm CMOS technology. Simulation results show that the flipping efficiency of the P-SSHI circuit is over 80% with an off-chip inductor value of 820 μH. The output power the proposed rectifier can obtain is 44.4 μW, which is 6.7× improvement compared to the maximum output power of a traditional rectifier. Both the active diodes and the P-SSHI help to improve the output power of the proposed rectifier. LDO outputs a voltage of 1.8 V with the maximum 90% power efficiency. The proposed P-SSHI rectifier interface circuit can be self-powered without the need for additional power supply.

A Dual Band RF Energy Harvester with Hybrid Threshold Voltage Self-Compensation

Threshold voltage self-compensation technology (TVSC) has been widely used in RF energy harvester. In this paper, the influence of the size of rectifying transistors, the stages and compensation orders of the rectifier, and the impedance matching network on the performance of RF energy harvester has been studied. A dual band RF energy harvester with hybrid threshold voltage self-compensation (HTVSC) is proposed in this paper in 65-nm CMOS process according to the distribution characteristic of the ambient RF energy. By combining TVSC and the technology of weak forward bias between the source and body of the rectifying transistor, the threshold voltage of MOSFET can be dramatically decreased. The performance of the RF energy harvester has been improved using this new technology. The simulation results show that the proposed dual band RF energy harvester can acquire energy at the band of 900MHz and 2.4GHz. At 900MHz-band (825–960MHz), with 1MΩ load resistor, the output voltage of the energy harvester can be over 1.0V with a minimum −18dBm RF input power and a maximum 13.8% power conversion efficiency (PCE). At 2.4GHz-band (2.4–2.485GHz), the minimum input power can be as low as −19dBm with a maximum efficiency of 16.8%.

A LOW OFFSET HIGH SPEED COMPARATOR FOR PIPELINE ADC

A low offset and high speed preamplifier latch comparator is proposed for high-speed pipeline analog-to-digital converters (ADCs). In order to realize low offset, both offset cancellation technique...

A CMOS 4.6ppm/°C curvature-compensated bandgap voltage reference

A novel high precision high order curvature-compensated bandgap reference (BGR) is presented in this paper designed using the subthreshold current of self-cascode transistors in standard digital 0.18 μm CMOS process. Simultaneously its temperature coefficient is typically 4.6 ppm/◦C in the temperature range of −25 to 120◦C with a supply current of 17.25μA. A power supply rejection ratio (PSRR) of −51 dB is achieved while the layout area is no more than 0.0022 mm2.

A high speed self-biased CMOS amplifier IP core

A novel high speed 0.25 /spl mu/m CMOS amplifier IP core is presented which use the complementary self-biasing differential amplifier technique. The proposed amplifier features a 418 MHz unity gain frequency and 375 V//spl mu/s slew rate with capacitive load 2pF. The output voltage of the proposed amplifier swings from Vgnd to Vdd and the static power less than 0.32 /spl mu/W. A Verilog-A behavioral model is presented for the amplifier IP core which contains the important non-idealities of the amplifier.