Junchao Mu

A Hybrid Threshold Self-compensation Rectifier for RF Energy Harvesting

This paper presents a novel highly efficient 5-stage RF rectifier in SMIC 65 nm standard CMOS process. To improve power conversion efficiency (PCE) and reduce the minimum input voltage, a hybrid threshold self-compensation approach is applied in this proposed RF rectifier, which combines the gate-bias threshold compensation with the body-effect compensation. The proposed circuit uses PMOSFET in all the stages except for the first stage to allow individual body-bias, which eliminates the need for triple-well technology. The presented RF rectifier exhibits a simulated maximum PCE of 30% at −16.7 dBm (20.25 μW) and produces 1.74V across 0.5MΩ load resistance. In the circumstances of 1MΩ load resistance, it outputs 1.5V DC voltage from a remarkably low input power level of −20.4 dBm (9 μW) RF input power with PCE of about 25%.

A high accuracy CMOS subthreshold voltage reference with offset cancellation and thermal compensation

This paper presents a high accuracy CMOS subthreshold voltage reference without BJTs for the low-supply-voltage and low-power application. The low supply voltage and low power dissipation are achieved, by making MOSFETs work in the subthreshold region. Besides, the offset scaling down (OSD) technique is proposed for the first time to cancel out the reference voltage variation caused by the offset of the clamping OTA. In addition, the pseudo-series-diodes are used with the negative temperature coefficient (TC) impendence for the second-order thermal compensation. Finally, the proposed voltage reference circuit is implemented in a standard 0.13m CMOS process, while the active silicon area is about 0.150.24mm2. At the minimum supply voltage 0.6V, the measured results shows a TC of 12.8ppm/C in the range of 2585C, and total power consumption of 373 nW. The line regulation is 0.15mV/V in the supply voltage range of 0.61.8V, and the variation of the reference voltage (/) is 1.28% without trimming and 0.42% after trimming, respectively. The power supply rejection ratio (PSRR) without any filtering capacitor at 1000Hz is 51dB for 0.6V supply and 73.8dB for 1.8V supply, respectively.

An Active Voltage Doubling Rectifier with Unbalanced-Biased Comparators for Piezoelectric Energy Harvesters

For wearable health monitoring systems, a fundamental problem is the limited space for storing energy, which can be translated into a short operational life. In this paper, a highly efficient active voltage doubling rectifier with a wide input range for micro-piezoelectric energy harvesting systems is proposed. To obtain a higher output voltage, the Dickson charge pump topology is chosen in this design. By replacing the passive diodes with unbalanced-biased comparator-controlled active counterparts, the proposed rectifier minimizes the voltage losses along the conduction path and solves the reverse leakage problem caused by conventional comparator-controlled active diodes. To improve the rectifier input voltage sensitivity and decrease the minimum operational input voltage, two low power common-gate comparators are introduced in the proposed design. To keep the comparator from oscillating, a positive feedback loop formed by the capacitor C is added to it. Based on the SMIC 0.18-μm standard CMOS process, the proposed rectifier is simulated and implemented. The area of the whole chip is 0.91×0.97 ㎟, while the rectifier core occupies only 13% of this area. The measured results show that the proposed rectifier can operate properly with input amplitudes ranging from 0.2 to 1.0V and with frequencies ranging from 20 to 3000 Hz. The proposed rectifier can achieve a 92.5% power conversion efficiency (PCE) with input amplitudes equal to 0.6 V at 200 Hz. The voltage conversion efficiency (VCE) is around 93% for input amplitudes greater than 0.3 V and load resistances larger than 20kΩ.

A Dual Band RF Energy Harvester with Hybrid Threshold Voltage Self-Compensation

Threshold voltage self-compensation technology (TVSC) has been widely used in RF energy harvester. In this paper, the influence of the size of rectifying transistors, the stages and compensation orders of the rectifier, and the impedance matching network on the performance of RF energy harvester has been studied. A dual band RF energy harvester with hybrid threshold voltage self-compensation (HTVSC) is proposed in this paper in 65-nm CMOS process according to the distribution characteristic of the ambient RF energy. By combining TVSC and the technology of weak forward bias between the source and body of the rectifying transistor, the threshold voltage of MOSFET can be dramatically decreased. The performance of the RF energy harvester has been improved using this new technology. The simulation results show that the proposed dual band RF energy harvester can acquire energy at the band of 900MHz and 2.4GHz. At 900MHz-band (825–960MHz), with 1MΩ load resistor, the output voltage of the energy harvester can be over 1.0V with a minimum −18dBm RF input power and a maximum 13.8% power conversion efficiency (PCE). At 2.4GHz-band (2.4–2.485GHz), the minimum input power can be as low as −19dBm with a maximum efficiency of 16.8%.

A Near-Threshold Voltage Startup Monolithic Boost Converter with Adaptive Sleeping Time Control

A novel near-threshold voltage startup monolithic boost converter is presented in this paper using an adaptive sleeping time control (ASTC) scheme for low-power applications. The proposed ASTC scheme can promote the power efficiency of the current-mode boost converter under light load by automatically adjusting the sleep time of the converter, and the converters quiescent current drops down to 4μA during the sleeping period. In addition, a new soft-start method is introduced to make the boost converter start up with a near-threshold input voltage. The proposed boost converter was fabricated in a standard 0.18μm CMOS process and occupies a small chip area of 0.50mm×1.22mm. Experimental results show that the boost converter achieves the minimum 0.5-V startup voltage when the output voltage is set to 1.8V. After startup, the input voltage range can be expanded from 0.3V to 1.5V with a switching frequency of 1MHz. In addition, a peak efficiency of 94% and a minimum efficiency of 81% are measured at the 1.5-V input voltage as the load current ranges from 0.1mA to 100mA.

A dual mode step-down switched-capacitor DC-DC converter with adaptive switch width modulation

Abstract This paper proposes a step-down switched-capacitor (SC) DC-DC converter with pulse frequency modulation (PFM) and burst mode. This design proposes a novel dual mode control strategy to achieve high performance over a wide load range. PFM is adopted at heavy load to achieve the small output voltage ripple while burst mode is adopted at light load to improve transient response and power efficiency. To further improve the efficiency, an adaptive switch width modulation (ASWM) is proposed to reduce switching losses. The measured results show that the proposed four conversion ratios converter can operate with a 2.0–3.6 V input voltage range, load current from 0 to 2 mA at the output voltage of 1.2 V. The peak power efficiency is up to 84.2% from a 2.7 V input voltage supply at a load current of 2 mA. At a load of 60 μA, the burst mode achieves an 11% maximum efficiency improvement, and the average efficiency improvement of 6% is achieved with ASWM.

A 0.5 V, 40nW voltage reference for WBAN devices

For WBAN (Wireless Body area network) devices, low supply voltage and high accuracy reference can reduce the power consumption of the whole circuit and prolong the battery life. This paper presents a 40nW, 0.5V supply voltage and 0.24V output reference for WBAN devices. The emitter-base voltage of a PNP transistor is divided by the switch capacitor circuit to obtain the low output reference. The resistor-less PTAT (proportional to absolute temperature) circuit and the low-voltage high PSRR (power supply rejection ratio) current source is used to improve the accuracy and line regulation performance of the reference. The proposed bandgap reference is implemented in 0.18μm standard CMOS process and has a total area of 0.058mm2. Test results show the minimum supply voltage is 0.5V. The line regulation is about 1.1mV/V in the supply voltage range of 0.5–0.9V. With 3-bit trimming, the TC (temperature coefficient) of 58 ppm/°C in the range of −25°C −85°C and the accuracy of 0.9% (3a) can be achieved.

A voltage doubling AC-DC converter with offset-controlled comparators for piezoelectric energy harvester

A highly efficient active voltage doubling rectifier with wide input range for micro-piezoelectric energy harvesting systems is proposed in this paper. By replacing the passive diodes in Dickson charge pump with offset-controlled comparator-based active counterparts, the proposed rectifier minimizes voltage drop along the conduction path and solves the reverse leakage problem caused by delay and mismatch of the conventional active diode. Based on SMIC 0.18μm standard CMOS process, the proposed rectifier is simulated and implemented. The measured results show that the rectifier can operate properly with input amplitudes from 0.2 V to 1.0V and frequencies from 20Hz to 3000Hz. With a 200Hz input of 0.6V amplitude, the proposed rectifier can achieve the peak power conversion efficiency (PCE) of 92.5%. When the input amplitude is greater than 0.3V and load resistance larger than 20kΩ, the voltage conversion efficiency (VCE) of at least 93% can be achieved.