Steven Dupont

A scalable 8.7nJ/bit 75.6Mb/s parallel concatenated convolutional (turbo-) CODEC

A 6 to 75.6Mb/s turbo CODEC with block size from 32 to 432, code rate from 1/3 to 3/4, 5.35/spl mu/s/block decoding latency and up to 8.25dB coding gain is described. This IC is fabricated in a 0.18/spl mu/m process and has a core area of 7.16mm/sup 2/. Energy-optimized architecture reduces the energy per bit to 8.7nJ and is almost constant over the throughput range.

A coarse-grained array based baseband processor for 100Mbps+ software defined radio

The software-defined radio (SDR) concept aims to enabling cost-effective multi-mode baseband solutions for wireless terminals. However, the growing complexity of new communication standards applying, e.g., multi-antenna transmission techniques, together with the reduced energy budget, is challenging SDR architectures. Coarse-grained array (CGA) processors are strong candidates to undertake both high performance and low power. The design of a candidate hybrid CGA-SEVID processor for an SDR baseband platform is presented. The processor, designed in TSMC 90 G process according to a dual-VT standard-cells flow, achieves a clock frequency of 400 MHz in worst case conditions and consumes maximally 310 mW active and 25 mW leakage power (typical conditions) when delivering up to 25,6 GOPS (16-bit). The mapping of a 20 MHz 2times2 MIMO-OFDM transmit and receive baseband functionality is detailed as an application case study, achieving 100 Mbps+ throughput with an average consumption of 220 mW.

A 80 Mb/s low-power scalable turbo codec core

Turbo coding has reached the step in which its astonishing coding gain is already being proven in real applications. Moreover, its applicability to future broadband communications systems is starting to be investigated. In order to be useful in this domain, special turbo codec architectures that cope with low latency, high throughput, low power consumption and high flexibility are needed. This paper presents an implementation of a convolutional turbo codec core based on innovative solutions for those requirements. The combination of a systematic data storage and transfer optimization with high and low level architectural solutions yields a final throughput up to 80.7 Mb/s, a decoding latency of 10 /spl mu/s and a power consumption of less than 50 nJ/bit. The 14.7 mm/sup 2/ full-duplex full-parallel core, implemented in a CMOS 0.18 /spl mu/m technology, is a complete flexible solution for broadband turbo coding.

A 10.37 mm2 675 mW reconfigurable LDPC and Turbo encoder and decoder for 802.11n, 802.16e and 3GPP-LTE

This paper describes the implementation of a flexible Turbo and LDPC outer modem engine which is capable of supporting the WiFi(802.11n), WiMax(802.16e) and 3GPPLTE standard on the same hardware resources. The chip is implemented in a 65nm CMOS technology and occupies 10.37 mm2. The decoder flexibility is offered by means of an application-specific instruction-set processor (ASIP), with full datapath reuse between Turbo and LDPC decoding. The encoders are dedicated ASIC datapaths. The maximum clock speed can be set to 320 MHz allowing a decoder output rate for a single iteration in excess of 140 Mbps for Turbo and 640 Mbps for LDPC with a maximum power consumption of 675 mW. The architecture template has been extended to support other standards like the DVB-S2/T2 LDPC decoding as well.

An integrated reconfigurable engine for multi-purpose sensing up to 6 GHz

We demonstrate a reconfigurable engine for multipurpose spectrum sensing within the cost and power constraints of mobile devices. The analog part builds up on the Scaldio reconfigurable analog front-end [1]. The digital part is an innovative Digital Front-end for Sensing capable of performing a range of sensing algorithms [3], which has now been fully implemented as a chip. The goal of this demo is the first demonstration of the digital chip, integrated with an analog front-end, enabling real-time validation of the sensing engine. The setup is validated for DVB-T and LTE, two important candidates for future DySPAN networks, as well as for very fast spectrum sweeping. This is the first integrated low power solution that can achieve such a very fast spectrum sweeping, thanks to the integration of two innovative components.

Hardware and a Tool Chain for ADRES

Until recently, only a compiler and a high-level simulator of the reconfigurable architecture ADRES existed. This paper focuses on the problems that needed to be solved when moving from a software-only view on the architecture to a real hardware implementation, as well as on the verification process of all involved tools.

An energy efficient 18Gbps LDPC decoding processor for 802.11ad in 28nm CMOS

The design of multi-Gbps LDPC decoder has become a hot topic in recent years as the demand of transformation towards 5G. An energy efficient 18Gbps LDPC decoder based on LDPC ASIP with half layer paralleled architecture is proposed. The feasibility of the design is proven by its demonstrator silicon in 28nm CMOS technology, with a record energy efficiency of 18.4 pJ/decoded bit and area efficiency of 23.8 Gbps/mm2 for the ½ coding rate working at 18.4Gbps. With frequency, voltage scaling and multi-core management, the decoder supports a wide range of throughput, from 1.8Gbps to 18.4Gbps. The measurement results show the ASIP based design not only provides an energy efficient high speed solution but also be competitive with published ASIC solution at low and medium throughput scenarios.