Lingpeng Guan

A fully integrated SOI RF MEMS technology for system-on-a-chip applications

In this paper, a silicon-on-insulator (SOI) radio-frequency (RF) microelectromechanical systems (MEMS) technology compatible with CMOS and high-voltage devices for system-on-a-chip applications is experimentally demonstrated for the first time. This technology allows the integration of RF MEMS switches with driver and processing circuits for single-chip communication applications. The SOI high-voltage device (0.7-/spl mu/m channel length, 2-/spl mu/m drift length, and over 35-V breakdown voltage), CMOS devices (0.7-/spl mu/m channel length and 1.3/-1.2 V threshold voltage), and RF MEMS capacitive switch (insertion loss 0.14 dB at 5 GHz and isolation 9.5 dB at 5 GHz) are designed and fabricated to show the feasibility of building fully integrated RF systems. The performance of the fabricated RF MEMS capacitive switches on low-resistivity and high-resistivity SOI substrates will also be compared.

A Novel Planar Power MOSFET With Laterally Uniform Body and Ion-Implanted JFET Region

A novel sub-20-V planar power MOSFET using ion implantation to form the body and JFET regions is proposed and experimentally demonstrated. The fabricated novel device has a breakdown voltage of 14 V and a threshold voltage of 0.57 V. Compared with conventional planar vertical double-diffused MOS devices, the specific on-resistance of the novel device is reduced by 32% because of the reduced JFET resistance. The threshold- voltage variation of the novel device is also characterized. The standard deviation of the threshold voltage is reduced from 36 mV of the conventional device to 10 mV of the novel device. This is because the channel region of the novel device is uniformly doped by using ion implantation. The gate-drain charge density is similar to that of the conventional device. The novel device is very promising for sub-20-V dc/dc conversion applications.

Fully integrated CMOS and high voltage compatible RF MEMS technology

In this paper, a fully integrated CMOS and high voltage compatible RF MEMS (radio frequency microelectromechanical systems) technology is proposed and demonstrated for the first time. The high performance RF MEMS switch, high voltage MOSFET, and CMOS devices are all obtained using a simple process. The fabricated high voltage device has a breakdown voltage of over 35V. The MEMS capacitive switch fabricated on a high resistivity SOI substrate and with high-k dielectric (HfO/sub 2/) exhibits a low insertion loss (0.14dB at 5GHz) and a good isolation (9.5dB at 5GHz). This technology demonstrates the feasibility of building fully integrated RF systems for wireless communication applications.

A Novel Sub-20V Power MOSFET with Improved On-Resistance and Threshold Variation

In this paper, a novel planar power MOSFET using ion implantation to form the body and JFET regions is presented. The novel device is compared with conventional planar VDMOS devices. The specific on-resistance is reduced by 32% due to the reduction in JFET resistance. The standard deviation of the threshold voltage is reduced from 36 to 10 mV, because the channel region of the novel device is uniformly doped by using ion implantation. The gate-drain charge density is similar, and there is a 28% reduction in the figure-of-merit. The breakdown and threshold voltages of the novel device are 14 and 0.57 V, respectively.

A 30 V Self-Aligned Metal/Poly-Si Replacement Gate Planar DMOS for DC/DC Converters

In this letter, a novel self-aligned metal/poly-Si gate planar double-diffused MOS (DMOS) is proposed and demonstrated for high-switching-speed and high-efficiency dc/dc converter applications. The self-aligned metal/poly-Si gate is realized by a replacement gate technology. The fabricated metal/poly-Si gate planar DMOS has a breakdown voltage of 36 V and a threshold voltage of 2.1 V. The gate sheet resistance of the metal/poly-Si gate is around 0.2 Omega/square, which is 50 times lower than that of the polysilicon gate. The low sheet resistance reduces the switching time as well as the power loss of the device during switching. For a device with a drain current of 69 A/cm2, the turn-on and turn-off times are reduced from 29 to 25 ns and from 36 to 31 ns, respectively. The turn-on and turn-off switching energy losses are reduced by 22% and 15%, respectively

A novel SOI lateral-power MOSFET with a self-aligned drift region

In this letter, a novel drift-region self-aligned SOI lateral-power MOSFET using a partial exposure technique is proposed and demonstrated for RF power amplifier applications. The drift self-aligned structure was achieved using a simple process and without the need of an additional mask. Furthermore, the drift length can be controlled conveniently using different layout designs. The fabricated SOI power device has a breakdown voltage of over 20 V. Using a 0.7-/spl mu/m nonsilicide technology, the cutoff frequency (f/sub t/) and maximum oscillation frequency (f/sub max/) of the device are 10.1 and 13.7 GHz, respectively.

A New Isolation Technology for Automotive Power-Integrated-Circuit Applications

In this paper, a new bulk silicon isolation structure with wafer-thick trenches is proposed for automotive (42 V) power-integrated-circuit applications. This technology provides the advantages of complete isolation with lower wafer cost and higher thermal-dissipation capability as compared with the silicon-on-insulator technology. Experimental results show that the new isolation structure can provide complete electrical isolation and with a 13% reduction in thermal resistance.

A novel drift region self-aligned SOI power MOSFET using a partial exposure technique

In this paper, a novel drift region self-aligned SOI power MOSFET using a partial exposure technique is proposed and demonstrated. The drift region is self-aligned to the channel and was achieved using a simple process without the need of an additional mask. Furthermore, the drift length can be controlled conveniently using different layout designs with a length ranging from 0.3/spl mu/m to a few microns. The fabricated SOI power device has a breakdown voltage of over 20V. Using a 0.7/spl mu/m non-silicide technology, the cutoff frequency (f/sub t/) and maximum oscillation frequency (f/sub max/) of the device are 10.1 GHz and 13.7GHz, respectively.

A New 20 V-Rated Buried-Oxide Trench-Gate Bipolar-Mode JFET FOR DC/DC Converters

A new normally-on buried-oxide (BOX) trench-gate bipolar-mode JFET (BTB-JFET) is reported for high-frequency low-voltage low-power-loss dc/dc converter applications. The BOX structure of the device is realized by localized thermal oxidation at the bottom of the gate trench. The fabricated BTB-JFET has a breakdown voltage of 21 V at VGS = -3 V. Due to the BOX under the gate region, the gate-drain capacitance CGD of the device is decreased by up to 30% at zero source-drain bias compared with that of the conventional trench-gate bipolar-mode JFET. The lower CGD reduces the switching times and the voltage dips during turn-on and turn-off. The resistive turn-on and turn-off times of the device are decreased from 31.5 to 30 ns and 12 to 10.5 ns, respectively. This approximately provides a 5% reduction in ton and 12% in toff, which is in agreement with the simulation results.

Transient Characterization of the Planar DMOS With a Metal/Poly-Si Replacement Gate

In this brief, transient characterization of a novel self-aligned metal/poly-Si gate planar double-diffused MOS (DMOS) transistor for high switching speed and high-efficiency dc/dc converter applications are reported. The breakdown voltage and the threshold voltage of the fabricated metal/poly-Si gate planar DMOS are 36 and 2.1 V, respectively. The gate sheet resistance of the metal/poly-Si gate is around 0.2 O/? , which is 50 times lower than that of the polysilicon gate. The low sheet resistance reduces the switching time, as well as the power loss of the device during the clamped inductive load switching. For a device with a drain current of 69 A/cm2, the turn-on and turn-off times are reduced from 29 to 25 ns and from 36 to 31 ns, respectively. The turn-on and turn-off switching energy losses are reduced by 22% and 15%, respectively.