Jacky C. W. Ng

A Novel Planar Power MOSFET With Laterally Uniform Body and Ion-Implanted JFET Region

A novel sub-20-V planar power MOSFET using ion implantation to form the body and JFET regions is proposed and experimentally demonstrated. The fabricated novel device has a breakdown voltage of 14 V and a threshold voltage of 0.57 V. Compared with conventional planar vertical double-diffused MOS devices, the specific on-resistance of the novel device is reduced by 32% because of the reduced JFET resistance. The threshold- voltage variation of the novel device is also characterized. The standard deviation of the threshold voltage is reduced from 36 mV of the conventional device to 10 mV of the novel device. This is because the channel region of the novel device is uniformly doped by using ion implantation. The gate-drain charge density is similar to that of the conventional device. The novel device is very promising for sub-20-V dc/dc conversion applications.

A Low-Voltage Planar Power MOSFET With a Segmented JFET Region

A new low-voltage planar power MOSFET with a segmented junction field effect transistor (JFET) region is proposed and demonstrated in this paper. The segmented JFET region consists of alternating n- and p-regions formed by using ion implantation, and it is fully depleted before the drain-source breakdown voltage is reached to provide a high breakdown voltage. The new planar power MOSFET allows a smaller gate-drain overlap area, a shallower p-body, and a JFET region with a doping concentration higher than those of the conventional vertical double-diffused MOSFETs (VDMOSFETs). The new structure with a breakdown voltage of 34 V is fabricated by using a 0.5-mum technology and is compared with the conventional VDMOSFET. The gate-drain charge density and the figure-of-merit are improved by 51% and 48%, respectively. However, the specific on-resistance of the device is increased by 5% due to the smaller conducting area in the segmented JFET region. Simulation results show that the figure-of-merit of the new structure is very favorable compared to those of commercial devices at the same voltage rating.

A Novel SONOS Gate Power MOSFET With Excellent UIS Capability

A novel silicon-oxide-nitride-oxide-silicon gate power MOSFET is proposed and experimentally demonstrated. In the novel device, the doping concentration of the p-body is increased by an order of magnitude compared to that of the conventional power MOSFET. However, the positive shift of the threshold voltage due to the heavily doped p-body is fully compensated by the positive fixed charges preprogrammed in the silicon nitride of the oxide-nitride-oxide gate dielectric. As a result, a normal threshold voltage can be obtained, and the avalanche energy absorption of the novel device at unclamped inductive switching is 5.2 times that of the conventional power MOSFET.

Extraction of the Inversion and Accumulation Layer Mobilities in n-Channel Trench DMOSFETs

A new method to extract both the inversion and accumulation layer mobilities of electrons in n-channel trench double-diffused MOSFETs (DMOSFETs) is proposed and implemented for the first time. First, a model is developed for the on-resistance of the n-channel trench DMOSFET. This on-resistance model is fitted to the experimental data measured from an experimental n-channel trench DMOSFET by the method of linear least squares fitting. A very good fit is obtained such that the average percentage error between the model curve and the experimental on-resistance is less than plusmn1%. The fitting parameters obtained are used to calculate the inversion and accumulation layer mobilities as a function of a wide range of effective electric field. The calculated mobilities agree with those previously reported for conventional MOSFETs. The results are useful for optimizing the performance and reliability of the trench DMOSFETs

A New Trench Power MOSFET With an Inverted L-Shaped Source Region

A new trench power MOSFET with an inverted L-shaped source region is proposed and experimentally demonstrated. The fabricated new device has a breakdown voltage of 54 V. The avalanche energy absorption of the new device at unclamped inductive switching is 2.1 times that of the fabricated conventional trench power MOSFET. This is due to the minimized n+-source/p-body junction in the structure. Moreover, the specific on-resistance of the new device is reduced by 30% due to the smaller pitch. The new device is very promising for automotive electric power steering applications.

UIS Analysis and Characterization of the SONOS Gate Power MOSFET

In this paper, unclamped inductive switching (UIS) performance of the novel silicon-oxide-nitride-oxide-silicon (SONOS) gate power MOSFET (SG-MOSFET) is analyzed. The avalanche energy absorption of the SG-MOSFET at UIS is 5.2 times that of the conventional power MOSFET. Analysis shows that the improvement is due to the heavily doped p-body used in the device. Moreover, the influence of the structural parameters on the UIS performance of the device is experimentally characterized. Measurement results show that the UIS performance is not sensitive to the p+ contact width and slightly degrades with a larger gate length. Furthermore, the results show that it is promising to further improve the UIS performance of the device by using a more efficient charge trapping material in the gate dielectric to allow further increase in the p-body doping concentration.

The Effect of Self-Heating in LDMOSFET Expansion Regime

In this paper, it is the first time that the effect of self-heating of LDMOS transistors operating in the so-called expansion regime of the output characteristics is studied. Experimental characterization and numerical simulations are used to demonstrate that, in order to explain the origin of the current enhancement phenomenon observed in the output characteristics of LDMOS transistors biased at high gate and drain voltages (which is named as the expansion regime), the thermal effect of the device self-heating, in addition to the proposed intrinsic MOSFET saturation, has to be considered. This is supported by analyzing the temperature, charged carrier velocity, impact ionization rate, and electric field at different positions in the LDMOS transistors biased at different gate and drain voltages.

High performance CMOS-compatible super-junction FINFETs for Sub-100V applications

A novel lateral super-junction power FINFET (SJ-FINFET) structure suitable for integration is presented to address the challenges associated with sub-100V applications. The proposed lateral SJ-FINFET structure is compatible with advanced SOI-CMOS and FINFET fabrication technologies. It employs a 3D corrugated MOS channel and alternating n/p drift region pillars to achieve a 30% reduction in specific on-resistance when compared to conventional planar gate SJ-LDMOSFETs.

UIS Analysis and Characterization of the Inverted L-Shaped Source Trench Power MOSFET

In this paper, the unclamped inductive switching (UIS) behavior of an inverted L-shaped source trench power MOSFET is numerically analyzed and experimentally characterized. The measured avalanche energy absorption at UIS of the new trench power MOSFET is 2.1 times that of the conventional trench power MOSFET. This is explained by numerical simulation, which shows that the voltage drop across the emitter/base junction in the parasitic bipolar junction transistor of the new structure is smaller than that of the conventional structure. The influence of structural and device size variation of the new trench power MOSFET on UIS performance is also investigated. Results show that the avalanche current density at UIS is a strong function of the p+-region width and the device size. Furthermore, the effect becomes very significant as the device size becomes very small.

A Novel Sub-20V Power MOSFET with Improved On-Resistance and Threshold Variation

In this paper, a novel planar power MOSFET using ion implantation to form the body and JFET regions is presented. The novel device is compared with conventional planar VDMOS devices. The specific on-resistance is reduced by 32% due to the reduction in JFET resistance. The standard deviation of the threshold voltage is reduced from 36 to 10 mV, because the channel region of the novel device is uniformly doped by using ion implantation. The gate-drain charge density is similar, and there is a 28% reduction in the figure-of-merit. The breakdown and threshold voltages of the novel device are 14 and 0.57 V, respectively.