Lino Velo

Ultralarge scale integrated metallization and interconnects

The use of copper interconnects enables higher speed, enhanced electromigration lifetime reliability, reduced power consumption, and ultimately reduced manufacturing cost for silicon integrated circuits. The formation of planarized inlaid copper interconnects requires sequential deposition of a continuous diffusion barrier layer followed by copper seed/fill deposition and chemical-mechanical polishing (CMP). In this article we present a vacuum-integrated cluster tool technology for deposition of a TaN barrier and copper seed/fill layers using metalorganic chemical vapor deposition (MOCVD). The MOCVD-based TaN layers deposited at substrate temperatures below 430 °C are highly conformal, have 800–1000 μΩ cm resistivity, have satisfactory adhesion to silicon dioxide, and provide superior diffusion barrier properties compared to Ta and TaN layers deposited by physical vapor deposition. The cluster MOCVD-Cu process is capable of depositing conformal and low-resistivity copper seed layers with satisfactory adhe...

Sensor fusion for ULSI manufacturing process control

An integrated sensor system for conductive layer deposition process control is presented. The process equipment employs a multizone illuminator and noninvasive sensors for dynamic process uniformity control, real-time process and end-pointing, and process diagnosis. Various modes of sensor fusion have been implemented for improved equipment/process performance. Several noninvasive in situ sensors developed and integrated in a rapid thermal chemical-vapor-deposition (CVD) system for CVD tungsten (CVD-W) process control and diagnosis are presented.<<ETX>>

Fast-cycle-time single-wafer IC manufacturing

Abstract This paper presents a demonstration of the total use of RTP for fast-cycle-time semiconductor IC production. The feasibility of eliminating batch processing for CMOS IC fabrication has been shown. Our fast-cycle-time flexible single-wafer minifactory contains 34 single-wafer processors having various combinations of at least 9 different in-situ process monitoring and control sensors. Forty device fabrication processes are done with these systems, the majority being Advanced Vacuum Processors (AVPs). Multiple combinations of process energy sources and in-situ sensors are used to perform many process steps. Vacuum wafer cassettes are used for transporting wafers in a clean environment between machines. All of the AVPs are driven and supervised by a computer-integrated manufacturing (CIM) system, with unit process recipe specifications passed to the AVP host computer for process execution and control. More than 40 AVP systems have been designed and built for applications in TIs advanced silicon integrated circuit and HgCdTe detector technologies. Rapid thermal processes have been developed for all the thermal fabrication steps required in two 0.35 μm CMOS technologies. These processes include thin dielectric growth (dry and wet rapid thermal oxidations), high-pressure field oxidation, high-pressure BPSG reflow, source/drain and gate anneals. CMOS well formation, TiN/TiSi2 react & anneal, forming-gas anneal, and rapid thermal chemical-vapor deposition (RTCVD) processes for amorphous silicon, polysilicon, tungsten, silicon dioxide, and silicon nitride. These RTPs cover a processing temperature range of 450°–1100°C. An integrated sensor system will also be presented for rapid thermal process control. The lamp-heated reactors employ multi-zone axisymmetric illuminators and noinvasive in-situ sensors for real-time process uniformity control and process/equipment diagnostics. Various modes of sensor fusion have been implemented for improved equipment/process control performance. Improved RTP control has been established throughout the integrated CMOS flows using a customized backside seal structure on epitaxial wafers. Complete sub-half-micron CMOS process integration and device manufacturing have been successfully demonstrated with all-RTP thermal processing. Source/drain RTP was shown to decrease the effect of back-end processing on both salicided and unsalicided CMOS 0.25 μm devices.

Single-Wafer Process Integration and Process Control Techniques

State-of-the-art semiconductor technologies employ thermal processing steps for various anneal, oxidation, and chemical vapor deposition (CVD) processes. Most of these fabrication processes have been dominated by hot-wall batch furnaces. Many other unit processes, however, are already performed in single-wafer processors. These include plasma etch, plasma-enhanced dielectric deposition, metal deposition, ion implantation, and microlithography. The advantages of single-wafer processing have been discussed elsewhere [1]. They have been primarily related to enhanced control of processing individual wafers, particularly as the diameter of silicon wafers has increased to 200 mm.

The use of rapid thermal processing to improve performance of sub-half micron CMOS with and without salicide

The dependence of performance and parasitic resistances on source/drain implant anneal conditions and on back-end-of-line maximum temperature is evaluated for (1) salicided CMOS using n/sup +//p/sup +/ poly gates with surface channel PMOS and for (2) unsalicided CMOS using all n/sup +/ poly gates with buried channel PMOS. The gate oxide thickness used is 6 nm. Both the NMOS and PMOS effective channel lengths are near 0.25 mu m. The results show that CMOS circuit design can include wide transistors and asymmetrically placed contacts if salicide is used with RTP anneal of source/drain and back-end-of-line temperatures no higher than 725 C.<<ETX>>