Steve S. Huang

Fast-cycle-time single-wafer IC manufacturing

Abstract This paper presents a demonstration of the total use of RTP for fast-cycle-time semiconductor IC production. The feasibility of eliminating batch processing for CMOS IC fabrication has been shown. Our fast-cycle-time flexible single-wafer minifactory contains 34 single-wafer processors having various combinations of at least 9 different in-situ process monitoring and control sensors. Forty device fabrication processes are done with these systems, the majority being Advanced Vacuum Processors (AVPs). Multiple combinations of process energy sources and in-situ sensors are used to perform many process steps. Vacuum wafer cassettes are used for transporting wafers in a clean environment between machines. All of the AVPs are driven and supervised by a computer-integrated manufacturing (CIM) system, with unit process recipe specifications passed to the AVP host computer for process execution and control. More than 40 AVP systems have been designed and built for applications in TIs advanced silicon integrated circuit and HgCdTe detector technologies. Rapid thermal processes have been developed for all the thermal fabrication steps required in two 0.35 μm CMOS technologies. These processes include thin dielectric growth (dry and wet rapid thermal oxidations), high-pressure field oxidation, high-pressure BPSG reflow, source/drain and gate anneals. CMOS well formation, TiN/TiSi2 react & anneal, forming-gas anneal, and rapid thermal chemical-vapor deposition (RTCVD) processes for amorphous silicon, polysilicon, tungsten, silicon dioxide, and silicon nitride. These RTPs cover a processing temperature range of 450°–1100°C. An integrated sensor system will also be presented for rapid thermal process control. The lamp-heated reactors employ multi-zone axisymmetric illuminators and noinvasive in-situ sensors for real-time process uniformity control and process/equipment diagnostics. Various modes of sensor fusion have been implemented for improved equipment/process control performance. Improved RTP control has been established throughout the integrated CMOS flows using a customized backside seal structure on epitaxial wafers. Complete sub-half-micron CMOS process integration and device manufacturing have been successfully demonstrated with all-RTP thermal processing. Source/drain RTP was shown to decrease the effect of back-end processing on both salicided and unsalicided CMOS 0.25 μm devices.