Habib Najm

Single-wafer integrated semiconductor device processing

The authors present an overview of various single-wafer fabrication techniques for integrated processing of microelectronic devices. Numerous processing modules, sensors, and associated fabrication processes have been developed for advanced semiconductor device manufacturing. The combination of single-wafer processing, cluster tools, sensors, and advanced factory control/computer-integrated manufacturing techniques provides a capability for flexible fast-cycle-time device manufacturing. Specific developments and results are described in the areas of dry/vapor-phase surface cleaning, epitaxy, plasma processing, rapid thermal processing, and in situ sensors. An integrated sub-half micrometer CMOS technology based on these single-wafer fabrication methods including rapid thermal processing is also described. >

Sensor fusion for ULSI manufacturing process control

An integrated sensor system for conductive layer deposition process control is presented. The process equipment employs a multizone illuminator and noninvasive sensors for dynamic process uniformity control, real-time process and end-pointing, and process diagnosis. Various modes of sensor fusion have been implemented for improved equipment/process performance. Several noninvasive in situ sensors developed and integrated in a rapid thermal chemical-vapor-deposition (CVD) system for CVD tungsten (CVD-W) process control and diagnosis are presented.<<ETX>>

Fast-cycle-time single-wafer IC manufacturing

Abstract This paper presents a demonstration of the total use of RTP for fast-cycle-time semiconductor IC production. The feasibility of eliminating batch processing for CMOS IC fabrication has been shown. Our fast-cycle-time flexible single-wafer minifactory contains 34 single-wafer processors having various combinations of at least 9 different in-situ process monitoring and control sensors. Forty device fabrication processes are done with these systems, the majority being Advanced Vacuum Processors (AVPs). Multiple combinations of process energy sources and in-situ sensors are used to perform many process steps. Vacuum wafer cassettes are used for transporting wafers in a clean environment between machines. All of the AVPs are driven and supervised by a computer-integrated manufacturing (CIM) system, with unit process recipe specifications passed to the AVP host computer for process execution and control. More than 40 AVP systems have been designed and built for applications in TIs advanced silicon integrated circuit and HgCdTe detector technologies. Rapid thermal processes have been developed for all the thermal fabrication steps required in two 0.35 μm CMOS technologies. These processes include thin dielectric growth (dry and wet rapid thermal oxidations), high-pressure field oxidation, high-pressure BPSG reflow, source/drain and gate anneals. CMOS well formation, TiN/TiSi2 react & anneal, forming-gas anneal, and rapid thermal chemical-vapor deposition (RTCVD) processes for amorphous silicon, polysilicon, tungsten, silicon dioxide, and silicon nitride. These RTPs cover a processing temperature range of 450°–1100°C. An integrated sensor system will also be presented for rapid thermal process control. The lamp-heated reactors employ multi-zone axisymmetric illuminators and noinvasive in-situ sensors for real-time process uniformity control and process/equipment diagnostics. Various modes of sensor fusion have been implemented for improved equipment/process control performance. Improved RTP control has been established throughout the integrated CMOS flows using a customized backside seal structure on epitaxial wafers. Complete sub-half-micron CMOS process integration and device manufacturing have been successfully demonstrated with all-RTP thermal processing. Source/drain RTP was shown to decrease the effect of back-end processing on both salicided and unsalicided CMOS 0.25 μm devices.

A Hybrid Vortex Method with Deterministic Diffusion

In the general class of particle methods, the vortex method is most convenient for modeling high Reynolds (Re) number vortex flows. This is particularly true because: (1) the Lagrangian solution of the Navier-Stokes equations eliminates the need to discretize the non-linear inertia terms, leading to good numerical stability at high Re, and (2) the restriction of computational elements to the regions of the flow exhibiting shear and finite vorticity leads to significant numerical efficiency.