Pr Chidambaram

Cost effective 28nm LP SoC technology optimized with circuit/device/process co-design for smart mobile devices

With newer technology nodes, circuit/device/process codesign is essential to realize the advantages of scaling. Leveraging co-design approach based on a well-established manufacturing flow, a cost effective 28 nm 4G SOC technology has been crafted. This 28 nm design strategy uses two sets of design rules and 7 different Vt cells with optimal power gating to achieve a 2.4× increase in gate density, 55% decrease in power and 30% gain in frequency with respect to the 45 nm counterpart. Relevant technical tradeoffs between the design/technology interactions are discussed to illustrate the codesign aspects.

Cost and power/performance optimized 20nm SoC technology for advanced mobile devices

A cost competitive 20nm technology node is described that enabled industry-first 20nm cellular modem chip with 2× peak data rates vs 28nm, and 2× carrier aggregation. Process and design enhancements for layout context optimization, and continuous process improvements resulted in 18% boost in circuit performance while simultaneously achieving >30% power reduction. 3 mask local interconnect and 64nm double patterning lower level metals - with yield-friendly single color pitch of 95nm and M1 special constructs with 90nm (=gate pitch) single color pitch for cell abutment - were used for achieving ~2× gate density. Single patterning 80nm pitch metal for routing levels was optimized for both density and performance. Active/passive device and double pattern metal mask count was optimized to reach process should-cost goals. Resulting technology provides cost reduction vs 28 HKMG per close to historical trend, and also cost-competitiveness vs 28 PolySiON. Leveraging of yield learning of this common back-end metallization results in up to 6 month pull-in of 16nm Finfet node yield ramp.

Technology-design-manufacturing co-optimization for advanced mobile SoCs

How to maintain the Moore’s Law scaling beyond the 193 immersion resolution limit is the key question semiconductor industry needs to answer in the near future. Process complexity will undoubtfully increase for 14nm node and beyond, which brings both challenges and opportunities for technology development. A vertically integrated design-technologymanufacturing co-optimization flow is desired to better address the complicated issues new process changes bring. In recent years smart mobile wireless devices have been the fastest growing consumer electronics market. Advanced mobile devices such as smartphones are complex systems with the overriding objective of providing the best userexperience value by harnessing all the technology innovations. Most critical system drivers are better system performance/power efficiency, cost effectiveness, and smaller form factors, which, in turns, drive the need of system design and solution with More-than-Moore innovations. Mobile system-on-chips (SoCs) has become the leading driver for semiconductor technology definition and manufacturing. Here we highlight how the co-optimization strategy influenced architecture, device/circuit, process technology and package, in the face of growing process cost/complexity and variability as well as design rule restrictions.

Analog/Mixed-Signal Design in FinFET Technologies

Consumer demand for low-power mobile ICs has propelled CMOS scaling to arrive at the fully depleted finFET with foundry offerings already available at 16/14, 10, and 7 nm. The compact three-dimensional structure of the finFET offers superior short-channel control that achieves digital power reduction while increasing device performance for a given area. As system-on-chip technology remains driven by logic and SRAM scaling needs, designers of analog/mixed-signal subsystems must continue to adapt to new technology constraints. We attempt to summarize the challenges and technology considerations encountered when we port analog/mixed-signal designs to a finFET node. At 16/14 nm and beyond, designers also face many implications from scaling innovations leading to the finFET.

Environment dependence of analog matching and design-process optimization on a 28LP SoC technology for smart mobile devices

Mismatch of analog circuits designed for mobile devices are studied with nanoprobing, pattern density, and inline monitoring using a 28LP SoC technology. Active layer density was found to be the root cause of high mismatch variation. Design guidelines, along with an interleaved design, are shown to improve mismatch for a given process flow.