Liyan Miao

Self-assembly patterning for sub-15nm half-pitch: a transition from lab to fab

Directed self-assembly is an emerging technology that to-date has been primarily driven by research efforts in university and corporate laboratory environments. Through these environments, we have seen many promising demonstrations of forming self-assembled structures with small half pitch (<15 nm), registration control, and various device-oriented shapes. Now, the attention turns to integrating these capabilities into a 300mm pilot fab, which can study directed selfassembly in the context of a semiconductor fabrication environment and equipment set. The primary aim of this study is to create a 300mm baseline process of record using a 12nm half-pitch PS-b-PMMA lamellae block copolymer in order to establish an initial measurement of the defect density due to inherent polymer phase separation defects such as dislocations and disclinations.

Directed self-assembly defectivity assessment. Part II

The main concern for the commercialization of directed self-assembly (DSA) for semiconductor manufacturing continues to be the uncertainty in capability and control of defect density. Our research investigates the defect densities of various DSA process applications in the context of a 300mm wafer fab cleanroom environment; this paper expands substantially on the previously published DSA defectivity study by reporting a defect density process window relative to chemical epitaxial pre-pattern registration lines; as well as investigated DSA based contact hole shrinking and report critical dimension statistics for the phase separated polymers before and after etch, along with positional accuracy measurements and missing via defect density.

Sidewall spacer quadruple patterning for 15nm half-pitch

193nm immersion lithography, with the single-exposure resolution limitation of half-pitch 38nm, has extended its patterning capability to about 20nm using the double-patterning technique[1]. Despite the non-trivial sub-20nm patterning challenges, several NAND Flash manufacturers are already pursuing for sub-16nm patterning technology. 25nm NAND flash memory has already begun production in 2010, and given the typical 2-year scaling cycle, sub-16nm NAND devices should see pilot or mass production as early as 2014. Using novel patterning techniques such as sidewall spacer quadruple patterning (upon 120nm to 128nm pitch using dry ArF lithography) or triple patterning (upon 90nm pitch using immersion ArF lithography), we are able to extend optical lithography to sub-16nm half-pitch and demonstrate the lithographic performance that can nearly meet the ITRS roadmap requirements. In this paper, we conduct an in-depth review and demonstration of sidewall spacer quadruple patterning; including 300mm wafer level data of the mean values and CDU along with a mathematical assessment of the various data pools for sub-16nm lines and spaces. By understanding which processes (lithography, deposition, and etch) define the critical dimension of each data pool, we can make predictions of CDU capability for the sidewall spacer quad patterning. Our VeritySEM4i CD SEM tool demonstrated high measurement yield during fully automated measurements, which enables accurate lines, spaces and CDU measurements of the sub-16nm. The patterns generated from the sidewall spacer quadruple patterning techniques are used as a hardmask to transfer sub-16nm lines and spaces patterns to underneath amorphous silicon and silicon oxide layers, or poly silicon layer for 1X STI or poly gate applications.

Self-aligned triple patterning for continuous IC scaling to half-pitch 15nm

A self-aligned triple patterning (SATP) process is proposed to extend 193nm immersion lithography to half-pitch 15nm patterning. SATP process combines lithography and spacer techniques in a different manner than the conventional selfaligned double patterning (SADP) by keeping the mandrel lines and the second spacers. Compared with other scaling candidates such as self-aligned quadruple patterning (SAQP), it can relax the overlay accuracy requirement of critical layers and reduce their process complexity by using less masks. A 3-mask SATP mandrel recession (SMR) technique is invented to relax the overlay requirement of critical layer patterning. We also successfully demonstrate a 2-mask SATP process concept for patterning critical layers that contain lines/spaces, pads and peripheral circuits, thus opening an opportunity to significantly reduce the process costs. If applied in deep nano-scale IC fabrication, SATP technique will have a fundamental impact on the design methodology of integrated circuits. Using both dry and immersion lithography, we have fabricated half-pitch 21nm and 15nm patterns with a SATP process. It is found that the mandrels (lines) co-defined by lithography and etch processes have worse line width roughness (LWR) than that of spacers, which poses a unique problem to CD control in IC design. As a major focus of our early-stage research, patterning small mandrels/lines in SATP process is a non-trivial challenge. Different materials have been screened and an optimal scheme of mandrel and spacer materials is necessary to meet key requirements (e.g., LER and CDU) of the lithographic performance.

Mandrel-based patterning: density multiplication techniques for 15nm nodes

In many ways, sidewall spacer double patterning has created a new paradigm for lithographic roadmaps. Instead of using lithography as the principal process for generating device features, the role of lithography becomes to generate a mandrel (a pre-pattern) off-of-which one will subsequently replicate patterns with various degrees of density multiplication. Under this new paradigm, the innovativeness of various density multiplication techniques is as critical to the scaling roadmap as the exposure tools themselves. Sidewall spacer double patterning was the first incarnation of mandrel based patterning; adopted quickly in NAND flash where layouts were simple and design space was focused. But today, the use of advanced automated decomposition tools are showing spacer based patterning solutions for very complex logic designs. Future incarnations can involve the use of laminated spacers to create quadruple patterning or by retaining the original mandrel as a method to obtain triple patterning. Directed self-assembly is yet another emerging embodiment of mandrel based patterning, where selfseparating polymers are registered and guided by the physical constraint of a mandrel or by chemical pre-pattern trails formed onto the substrate. In this summary of several bodies of work, we will review several wafer level demonstrations, all of which use various forms of mandrel or stencil based density multiplication including sidewall spacer based double, triple and quadruple patterning techniques for lines, SADP for via multiplication, and some directed self-assembly results all capable of addressing 15nm technology node requirements and below. To address concerns surrounding spacer double patterning design restrictions, we show collaboration results with an EDA partner to demonstrate SADP capability for BEOL routing layers. To show the ultimate realization of SADP, we partner with IMEC on multiple demonstrations of EUV+SADP.

Challenges of 29nm Half-Pitch NAND FLASH STI Patterning with 193nm Dry Lithography and Self-Aligned Double Patterning

High NA (1.35) Immersion litho runs into the fundamental limit of printing at 40-45nm half pitch (HP). The next generation EUVL tool is known to be ready not until year 2012. Double patterning (DP) technology has been identified as the extension of optical photolithography technologies to 3xnm and 2xnm half-pitch for the low k1 regime to fill in the gap between Immersion lithography and EUVL. Self Aligned Double Patterning (SADP) Technology utilized mature process technology to reduce risk and faster time to market to support the continuation of Moores Law of Scaling to reduce the cost/function. SADP uses spacer to do the pitch splitting bypass the conventional double patterning (e.g. Litho-Freeze-Litho-Etch (LFLE), or Litho-Etch-Litho-Etch (LELE)) overlay problem. Having a tight overlay performance is extremely critical for NAND Flash manufacturers to achieve a fast yield ramp in production. This paper describes the challenges and accomplishment of a Line-By-Spacer (LBS) SADP scheme to pattern the 29nm half-pitch NAND Flash STI application. A 193nm Dry lithography was chosen to pattern on top of the amorphous carbon (a-C) film stack. The resist pattern will be transferred on the top a-C core layer follow by spacer deposition and etch to achieve the pitch splitting. Then the spacer will be used to transfer to the bottom a-C universal hardmask. This high selectivity a-C hardmask will be used to transfer the 29nm half-pitch pattern to the STI. Good within wafer CD uniformity (CDU) <2nm and line width roughness (LWR) <2nm for the 29nm half-pitch NAND FLASH STI were demonstrated as the benefits using double amorphous carbon hardmask layers. The relationships among the photoresist CDs, CD trimming , as-deposited spacer film thickness, spacer width and the final STI line/core space/gap space CDs will also be discussed in this paper since patterning is combining both lithography performance with CVD and Etch process performance. Film selection for amorphous carbon and the complete DP hardmask scheme in terms of etching selectivity, optical properties and stress optimization was another key challenge to balance excellent litho alignment signal strength and straight pattern profiles without line bending effects. Etching efforts also played a very important roll to obtain pattern integrality under such a high aspect ratio (> 10) case through the whole SADP process. Finally, cost analysis for 193nm dry lithography SADP will be compared to 193nm Immersion lithography SADP.

Demonstration of 32nm half-pitch electrical testable NAND FLASH patterns using self-aligned double patterning

Self-Aligned Double patterning (SADP) technology has been identified as the main stream patterning technique for NAND FLASH manufacturers for 3xnm and beyond. This paper demonstrates the successful fabrication of 32nm halfpitch electrical testable NAND FLASH wordline structures using a 3-mask flow. This 3-mask flow includes one critical lithography step and two non-critical lithography steps. It uses a positive tone (spacer as mask) approach to create 32nm doped poly wordlines. Electrical measurements of line resistance are performed on these doped poly wordlines to demonstrate the capability of this patterning technique. Detailed results and critical process considerations, including lithography, deposition and etch, will be discussed in this paper.

Post-Litho Line Edge/Width Roughness Smoothing by Ion Implantations

Solving the issue of line edge/width roughness (LER/LWR) in chip manufacturing is becoming increasingly urgent as the feature size continues to decrease. Several post-lithography processing techniques have been investigated by the semiconductor industry, but they were often proved to be inadequate in one area or another. In this study, a near isotropic ion implantation process, called Plasma Ribbon Beam Technology, was tuned for photoresist treatment and used to reduce LER/LWR by >30% while minimizing loss in the critical dimension (CD). Different implantation chemistries were evaluated and process parameters including energy, angle, beam current, and dose, were optimized. The LER/LWR measurement was performed on an SEM system designed for CD metrology. SEM images with resist lines of 3μm long were taken to capture more low frequency data. The results showed that, with Ar implantation on 193/193i photoresists, a 27-37% before-etch reduction in LER/LWR was achieved on 65nm and 45nm half-pitch lines whereas the CD change was controlled under ±1%. Preliminary test results on EUV photoresists have demonstrated similar trend. Compared to untreated photoresist, the LER/LWR power spectral density (PSD) data showed more than a half decade improvement in both the mid-frequency and low-frequency range. The significant low-frequency improvement affords this technique a unique advantage over other competing approaches. Pattern transfer of the LER/LWR improvements has been successfully demonstrated on 193/193i resists using both inorganic and organic ARC (anti-reflective coating).

Spatial frequency multiplication techniques towards half-pitch 10nm patterning

Novel patterning approaches are explored to enable either more cost-effective manufacturing solutions or a potential paradigm shift in patterning technology. First, a simplified self-aligned quadruple patterning (SAQP) process is developed to extend 193nm immersion lithography to half-pitch 10nm patterning. A detailed comparison with other SAQP schemes is made, and we find the simplified SAQP process can significantly reduce process complexity and costs. On the other hand, the topographic effect on the spacer width causes difficulty in obtaining lines with equal CD, thus a CVD/etch solution must be searched to meet the CDU requirement. Moreover, a motion-induced frequency multiplication (MIFEM) concept is proposed; and specifically, we develop a stress-induced frequency multiplication (SIFEM) technique to produce half-pitch 9nm lines/spaces with no need of ebeam, imprint, or self-assembly technology. It allows us to apply standard semiconductor fabrication processes and equipment to drive down the half pitch of a spatially periodic pattern below 10nm. The resolution of this patterning technique is dependent on the CD of spacers and their gaps regardless of optical resolution of the lithographic tool. The final space CD is mainly related with the material property of the fluid used in SIFEM process. The main issues of SIFEM process include: adjusting the fluid property to tune the gap CD, designing the anchor structures and line route to control the strength and direction of film stress, and overlay methodology development, etc.

Self-Aligned Double Patterning Process for 32/32nm Contact/Space and beyond using 193 Immersion Lithography

State of the art production single print lithography for contact is limited to ~43-44nm half-pitch given the parameters in the classic photolithography resolution formula for contacts in 193 immersion tool (k1 ≥ 0.3, NA = 1.35, and λ = 193nm). Single print lithography limitations can be overcome by (1) Process / Integration based techniques such as double-printing (DP), and spacer based self-aligned double patterning (SADP), (2) Non-standard printing techniques such as electron-beam (eBeam), extreme ultraviolet lithography (EUVL), nano-imprint Lithography (NIL). EUV tools are under development, while nanoimprint is a developmental tool only. Spacer based SADP for equal line/space is well documented as successful patterning technique for 3xnm and beyond. In this paper, we present an adaptation of selfaligned double patterning process to 2-D regular 32/32nm contact/space array. Using SADP process, we successfully achieved an equal contact/space of 32/32nm using 193 immersion lithography that is only capable of 43-44nm resolvable half-pitch contact printing. The key and unique innovation of this work is the use of a 2-D (x and y axis) pillar structure to achieve equal contact/space. Final result is a dense contact array of 32nm half-pitch in 2-D structure (x and y axis). This is achieved on simplified stack of Substrate / APF / Nitride. Further transfer of this new contact pattern from nitride to the substrate (e.g., Oxide, APF, Poly, Si...) is possible. The technique is potentially extendible to 22/22nm contact/space and beyond.