mou Xu

Self-aligned triple patterning for continuous IC scaling to half-pitch 15nm

A self-aligned triple patterning (SATP) process is proposed to extend 193nm immersion lithography to half-pitch 15nm patterning. SATP process combines lithography and spacer techniques in a different manner than the conventional selfaligned double patterning (SADP) by keeping the mandrel lines and the second spacers. Compared with other scaling candidates such as self-aligned quadruple patterning (SAQP), it can relax the overlay accuracy requirement of critical layers and reduce their process complexity by using less masks. A 3-mask SATP mandrel recession (SMR) technique is invented to relax the overlay requirement of critical layer patterning. We also successfully demonstrate a 2-mask SATP process concept for patterning critical layers that contain lines/spaces, pads and peripheral circuits, thus opening an opportunity to significantly reduce the process costs. If applied in deep nano-scale IC fabrication, SATP technique will have a fundamental impact on the design methodology of integrated circuits. Using both dry and immersion lithography, we have fabricated half-pitch 21nm and 15nm patterns with a SATP process. It is found that the mandrels (lines) co-defined by lithography and etch processes have worse line width roughness (LWR) than that of spacers, which poses a unique problem to CD control in IC design. As a major focus of our early-stage research, patterning small mandrels/lines in SATP process is a non-trivial challenge. Different materials have been screened and an optimal scheme of mandrel and spacer materials is necessary to meet key requirements (e.g., LER and CDU) of the lithographic performance.

Demonstration of 32nm half-pitch electrical testable NAND FLASH patterns using self-aligned double patterning

Self-Aligned Double patterning (SADP) technology has been identified as the main stream patterning technique for NAND FLASH manufacturers for 3xnm and beyond. This paper demonstrates the successful fabrication of 32nm halfpitch electrical testable NAND FLASH wordline structures using a 3-mask flow. This 3-mask flow includes one critical lithography step and two non-critical lithography steps. It uses a positive tone (spacer as mask) approach to create 32nm doped poly wordlines. Electrical measurements of line resistance are performed on these doped poly wordlines to demonstrate the capability of this patterning technique. Detailed results and critical process considerations, including lithography, deposition and etch, will be discussed in this paper.

Double patterning combined with shrink technique to extend ArF lithography for contact holes to 22nm node and beyond

Lithography becomes much more challenging when CD shrinks to 22nm nodes. Since EUV is not ready, double patterning combined with Resolution Enhancement Technology (RET) such as shrink techniques seems to be the most possible solution. Companies such as TSMC[1] and IBM[2] etc. are pushing out EUV to extend immersion ArF lithography to 32nm/22nm nodes. Last year, we presented our development work on 32nm node contact (50nm hole at 100nm pitch) using dry ArF lithography by double patterning with SAFIER shrink process[3]. To continue the work, we further extend our dry litho capability towards the 22nm node. We demonstrated double patterning capability of 40nm holes at 80nm pitch using ASML XT1400E scanner. It seems difficult to print pitches below 140nm on dry scanner in single exposure which is transferred into 70nm pitch with double patterning. To push the resolution to 22nm node and beyond, we developed ArF immersion process on ASML XT1700i-P system at the College of Nanoscale Science and Engineering (Albany, NY) combined with a SAFIER process. We achieved single exposure process capability of 25nm holes at 128nm pitch after shrink. It enables us to print ~25nm holes at pitch of 64nm with double patterning. Two types of hard mask (HM), i.e. TIN and a-Si were used in both dry and immersion ArF DP processes. The double patterning process consists of two HM litho-shrink-etch steps. The dense feature is designed into two complementary parts on two masks such that the density is reduced by half and minimum pitch is increased by at least a factor of 21/2 depending on design. The complete pattern is formed after the two HM litho-shrink-etch steps are finished.

Spatial frequency multiplication techniques towards half-pitch 10nm patterning

Novel patterning approaches are explored to enable either more cost-effective manufacturing solutions or a potential paradigm shift in patterning technology. First, a simplified self-aligned quadruple patterning (SAQP) process is developed to extend 193nm immersion lithography to half-pitch 10nm patterning. A detailed comparison with other SAQP schemes is made, and we find the simplified SAQP process can significantly reduce process complexity and costs. On the other hand, the topographic effect on the spacer width causes difficulty in obtaining lines with equal CD, thus a CVD/etch solution must be searched to meet the CDU requirement. Moreover, a motion-induced frequency multiplication (MIFEM) concept is proposed; and specifically, we develop a stress-induced frequency multiplication (SIFEM) technique to produce half-pitch 9nm lines/spaces with no need of ebeam, imprint, or self-assembly technology. It allows us to apply standard semiconductor fabrication processes and equipment to drive down the half pitch of a spatially periodic pattern below 10nm. The resolution of this patterning technique is dependent on the CD of spacers and their gaps regardless of optical resolution of the lithographic tool. The final space CD is mainly related with the material property of the fluid used in SIFEM process. The main issues of SIFEM process include: adjusting the fluid property to tune the gap CD, designing the anchor structures and line route to control the strength and direction of film stress, and overlay methodology development, etc.

Alignment and overlay improvements for 3x nm and beyond process with CVD sidewall spacer double patterning

Sidewall Spacer Double Patterning (SSDP) has been adopted for the primary patterning technique for 3x nm technology node and beyond in flash memory device manufacturing. Three mask flow are used in SSDP process scheme in order to form the actual device layer; Core mask to define the template pattern, Trim mask to cut (cropping) the unneeded line ends from sidewall spacer, and Pad mask to pattern the periphery structures. Inter-layer and intra-layers alignment with sidewall spacer double patterning requires some engineering efforts compared to traditional single patterning alignment techniques. In this paper, we study the impacts of hard-mask materials on the inter-layer alignment as well as the mark design and process flow impact on intra-layer alignment. For intra-layer alignment, we searched various ASML ATHENA alignment marks and found the only workable mark (VSPM-AA157 Polar). Although the wafer quality scores during alignment were less than 0.1% in many cases, the alignment was successful and yielded acceptable performance for research and development activities requiring less than 10nm misalignment. Further new mark design and test should be carried in implementing in sidewall spacer double patterning process.

Sub-20 nm trench patterning with a hybrid chemical shrink and SAFIER process

Chemical shrink and SAFIER are two resist shrinking processes that have been proved effective to reduce the trench and contact hole CD with enhanced resolution and process windows. Patterning sub-20 nm trenches, however, is found to be challenging using a single shrink process. To shrink resist trenches from 40-60 nm to sub-20 nm, a double shrink process seems more promising and we have studied the double chemical shrink, double SAFIER, and other possibilities. It is found that SAFIER process is capable of shrinking trenches by more than 30 nm with improved LER, but it suffers from severe CD non-uniformity (e.g., much smaller trenches at wafer center) induced by high SAFIER bake temperature applied to resists to obtain large shrinkage. Chemical shrink can also result in a fairly large shrinkage at high bake temperature, but LER is poor with no improvement in CDU. A novel hybrid process to combine chemical shrink (first) and SAFIER (last) together is proposed and developed. We find that this hybrid approach avoids the disadvantages of two mentioned shrinking processes and has the capability of patterning sub-20 nm trenches in resists with manufacturable process window, CDU and LER. Oxide and nitride etching process with APF (Advanced Patterning Film) as a hard mask is developed and sub-20 nm oxide/nitride trench patterning with excellent LER and acceptable CDU is achieved. APF hard mask is found to significantly improve CDU and LER of small trenches. Relations between CD/shrinkage and process temperature, pitch, and mask trench CD are investigated and the experimental results will be presented in this paper.

RET application in 45-nm node and 32-nm node contact hole dry ArF lithography process development

It is challenging to develop 45nm node contact hole using dry ArF lithography process with acceptable lithographic margin due to small process window and large mask error enhancement factor (MEEF). No single process using conventional lithography without resolution enhancement technique (RET) application will meet DOF requirement of 45nm node contact hole. We have developed dry ArF lithography processes for 45nm node contact hole on scanner ASML XT1400E by applying RETs including off-axis illumination, SAFIER (Shrink Assist Film for Enhanced Resolution) process, EFESE (focus scan), etc. The paper will discuss process window through pitches with optimized illumination, and where to separate pitches in case of double exposure with consideration of DOF and OPC model simulation. It will look into the effect of EFESE on DOF improvement, proximity, and MEEF at various pitches. The paper will also discuss OPC modeling strategy for 45nm node contact/via hole. It will analyze the effect of OPC grid size on OPC run time, file size, and edge placement error (EPE). To extend process further to 32nm node, we demonstrated the process capability for 32nm node hole using double patterning technique. We achieved 50nm final hole CD with pitch of 100nm. A hard mask (HM) technique was implemented in the process. The dense feature is designed into two complementary parts on two masks such that the density is reduced by half and minimum pitch is increased by at least a factor of 21/2 depending on design. The complete patters are formed with two litho-etch process steps. After the first mask litho process, the HM is etched. Then the second mask litho process is carried out and followed by a second HM etch and main etch.

Model calibration and slit position effect on full-mask process and proximity correction for extreme ultraviolet lithography

Extreme ultra-violet (EUV) lithography is a promising solution for semiconductor manufacturing for the 1Xnm node and beyond. Due to the mask shadowing effect and strong flare, process and proximity correction (PPC) is required for EUV lithography even though the k1 factor is much larger than that in current 193nm immersion lithography. In this paper, we will report a procedure of model calibration and full-mask PPC flow for EUV lithography. To calibrate the EUV model, identical test structures are placed at various locations on the mask across the slit direction. Slit position effect, including mask shadowing effect, will be investigated at different locations. The wafer is patterned with a 0.25 NA EUV scanner and measured with CD-SEM for process evaluation and PPC model calibration. The EUV model is verified by wafer measurements. A PPC flow with mask shadowing effect compensation and model-based flare compensation is introduced to perform full-mask correction for the BEOL flow at 30nm HP L/S for the 16nm technology node. The slit position effect on PPC is investigated through post-PPC verification.

Recessive self-aligned double patterning with gap-fill technology

In this paper, a recessive self-aligned double patterning (RSADP) process enabled by gap-fill technology is proposed and developed for BEOL applications. FEOL application is also possible by adding gap-fill/CMP steps to reverse the tone of contact/trench patterns. Compared with positive-tone spacer self-aligned double patterning (SADP), RSADP technique can reduce the process complexity by using less masks to pattern 2-D features. With a RSADP process, we successfully demonstrate (half-pitch) 50nm contact and 30nm line/space patterns using dry lithography.