Raymond Hung

Sidewall spacer quadruple patterning for 15nm half-pitch

193nm immersion lithography, with the single-exposure resolution limitation of half-pitch 38nm, has extended its patterning capability to about 20nm using the double-patterning technique[1]. Despite the non-trivial sub-20nm patterning challenges, several NAND Flash manufacturers are already pursuing for sub-16nm patterning technology. 25nm NAND flash memory has already begun production in 2010, and given the typical 2-year scaling cycle, sub-16nm NAND devices should see pilot or mass production as early as 2014. Using novel patterning techniques such as sidewall spacer quadruple patterning (upon 120nm to 128nm pitch using dry ArF lithography) or triple patterning (upon 90nm pitch using immersion ArF lithography), we are able to extend optical lithography to sub-16nm half-pitch and demonstrate the lithographic performance that can nearly meet the ITRS roadmap requirements. In this paper, we conduct an in-depth review and demonstration of sidewall spacer quadruple patterning; including 300mm wafer level data of the mean values and CDU along with a mathematical assessment of the various data pools for sub-16nm lines and spaces. By understanding which processes (lithography, deposition, and etch) define the critical dimension of each data pool, we can make predictions of CDU capability for the sidewall spacer quad patterning. Our VeritySEM4i CD SEM tool demonstrated high measurement yield during fully automated measurements, which enables accurate lines, spaces and CDU measurements of the sub-16nm. The patterns generated from the sidewall spacer quadruple patterning techniques are used as a hardmask to transfer sub-16nm lines and spaces patterns to underneath amorphous silicon and silicon oxide layers, or poly silicon layer for 1X STI or poly gate applications.

Self-aligned triple patterning for continuous IC scaling to half-pitch 15nm

A self-aligned triple patterning (SATP) process is proposed to extend 193nm immersion lithography to half-pitch 15nm patterning. SATP process combines lithography and spacer techniques in a different manner than the conventional selfaligned double patterning (SADP) by keeping the mandrel lines and the second spacers. Compared with other scaling candidates such as self-aligned quadruple patterning (SAQP), it can relax the overlay accuracy requirement of critical layers and reduce their process complexity by using less masks. A 3-mask SATP mandrel recession (SMR) technique is invented to relax the overlay requirement of critical layer patterning. We also successfully demonstrate a 2-mask SATP process concept for patterning critical layers that contain lines/spaces, pads and peripheral circuits, thus opening an opportunity to significantly reduce the process costs. If applied in deep nano-scale IC fabrication, SATP technique will have a fundamental impact on the design methodology of integrated circuits. Using both dry and immersion lithography, we have fabricated half-pitch 21nm and 15nm patterns with a SATP process. It is found that the mandrels (lines) co-defined by lithography and etch processes have worse line width roughness (LWR) than that of spacers, which poses a unique problem to CD control in IC design. As a major focus of our early-stage research, patterning small mandrels/lines in SATP process is a non-trivial challenge. Different materials have been screened and an optimal scheme of mandrel and spacer materials is necessary to meet key requirements (e.g., LER and CDU) of the lithographic performance.

Ultra-low contact resistivity with highly doped Si:P contact for nMOSFET

We report a record setting low NMOS contact Rc of 2e-9 Ωcm2 with an all-silicon based solution. The ultra-low contact resistivity of Ti/Si system of 2e-9 Ωcm2 has been demonstrated with Highly Doped Si:P (HD Si:P) EPI layer which is compatible with FinFET S/D structures combined with millisecond laser anneal activation (DSA). Additionally, we show the pathway to further improve contact resistivity with HD Si:P using P implantation followed by laser anneal to reach the contact resistivity requirement for the 10nm or 7 nm nodes.

Demonstration of 32nm half-pitch electrical testable NAND FLASH patterns using self-aligned double patterning

Self-Aligned Double patterning (SADP) technology has been identified as the main stream patterning technique for NAND FLASH manufacturers for 3xnm and beyond. This paper demonstrates the successful fabrication of 32nm halfpitch electrical testable NAND FLASH wordline structures using a 3-mask flow. This 3-mask flow includes one critical lithography step and two non-critical lithography steps. It uses a positive tone (spacer as mask) approach to create 32nm doped poly wordlines. Electrical measurements of line resistance are performed on these doped poly wordlines to demonstrate the capability of this patterning technique. Detailed results and critical process considerations, including lithography, deposition and etch, will be discussed in this paper.

Gate-first TiAlN P-gate electrode for cost effective high-k metal gate implementation

Gate-first (GF) high-k metal gate (HKMG) for LSTP/LOP logic and DRAM periphery applications requires an efficient and low-cost effective work function (eWF) solution. We demonstrated TiAlN for pFET eWF tuning without appreciable EOT, Jg, and interface degradation. Hence TiAlN is shown to be a key enabler to realize process-friendly and cost-effective GF HKMG implementation.

Spatial frequency multiplication techniques towards half-pitch 10nm patterning

Novel patterning approaches are explored to enable either more cost-effective manufacturing solutions or a potential paradigm shift in patterning technology. First, a simplified self-aligned quadruple patterning (SAQP) process is developed to extend 193nm immersion lithography to half-pitch 10nm patterning. A detailed comparison with other SAQP schemes is made, and we find the simplified SAQP process can significantly reduce process complexity and costs. On the other hand, the topographic effect on the spacer width causes difficulty in obtaining lines with equal CD, thus a CVD/etch solution must be searched to meet the CDU requirement. Moreover, a motion-induced frequency multiplication (MIFEM) concept is proposed; and specifically, we develop a stress-induced frequency multiplication (SIFEM) technique to produce half-pitch 9nm lines/spaces with no need of ebeam, imprint, or self-assembly technology. It allows us to apply standard semiconductor fabrication processes and equipment to drive down the half pitch of a spatially periodic pattern below 10nm. The resolution of this patterning technique is dependent on the CD of spacers and their gaps regardless of optical resolution of the lithographic tool. The final space CD is mainly related with the material property of the fluid used in SIFEM process. The main issues of SIFEM process include: adjusting the fluid property to tune the gap CD, designing the anchor structures and line route to control the strength and direction of film stress, and overlay methodology development, etc.

Ultra-low NMOS contact resistivity using a novel plasma-based DSS implant and laser anneal for post 7 nm nodes

We report a record-setting low NMOS contact resistivity of 1.2×10^-9 Ωcm² compatible with Ti/Si system and dopant segregation Schottky (DSS) based solution. The ultra-low contact resistivity of Ti/Si system is demonstrated with Highly Doped Si:P Epi layer and P implantation using conformal plasma implant followed by millisecond laser anneal. Additionally, we show that short-pulse nanosecond laser as post implant anneal provides a promising pathway to further improve NMOS ρ_C to below 1×10^-9 Ωcm² for the post 7 nm nodes.

PMOS contact resistance solution compatible to CMOS integration for 7 nm node and beyond

We report a PMOS contact resistivity (pc) improvement strategy by forming Ge-rich contact interface which is compatible to Ti/Si(Ge) system and CMOS integration flow. Short pulsed (nsec) laser anneal and advanced treatment during pre-clean have shown to be effective to segregate Ge towards SiGe surface resulting in PMOS ρc improvement. With Ge% increasing from 45 to 100%, pc improved three-fold, from 1.2e-8 to 2.8e-9 Ωcm2, due to bandgap modulation and preferred Fermi-level pinning [1]. In the end, we propose a CMOS-integration-compatible contact flow which addresses ρc optimization for both PMOS and NMOS contact.

Improving Tungsten gap-fill for advanced contact metallization

The requirement for Tungsten (W) seamless gap-fill becomes more critical and more challenging as the semiconductor industry moves to 10nm and beyond. Few reports can be found discussing the progress in tackling the challenge of reducing or eliminating the seam typical in W fill processes. This work introduces a breakthrough W chemical vapor deposition (CVD) process for gap-fill improvement and seam suppression. In this novel process, W material can be selectively deposited inside the structure than on the field, thus seam suppressed or even bottom-up fill can be achieved. Electrical results of line resistance reduction are presented. This selective process provides a state-of-the art approach to extend W fill technology for future scaling of advanced Logic and Memory technologies.

Threshold voltage tuning by metal gate work function modulation for 10 nm CMOS integration and beyond

This paper describes a novel scheme of metal gate integration to achieve precise threshold voltage (VTH) control and multiple VTH, by using metal composition and ion implantation (I/I) into work function metal (WFM). Moreover, WFM full fill is demonstrated with in situ barrier metal to satisfy the conductance requirement of sub-10 nm node gate.