Lovejeet Singh

32nm Overlay Improvement Capabilities

The industry is facing a major challenge looking forward on the technology roadmap with respect to overlay control. Immersion lithography has established itself as the POR for 45nm and for the next few nodes. As the gap closes between scanner capability and device requirements new methodologies need to be taken into consideration. Double patterning lithography is an approach thats being considered for 32 and below, but it creates very strict demands for overlay performance. The fact that a single layer device will need to be patterned using two sequential single processes creates a strong coupling between the 1st and 2nd exposure. The coupling effect during the double patterning process results in extremely tight tolerances for overlay error and scanner capabilities. The purpose of this paper is to explore a new modeling method to improve lithography performance for the 32nm node. Not necessarily unique for double patterning, but as a general approach to improve overlay performance regardless of which patterning process is implemented. We will achieve this by performing an in depth source of variance analysis of current scanner performance and project the anticipated improvements from our new modeling approach. Since the new modeling approach will involve 2nd and 3rd order corrections we will also provide and analysis that outlines current metrology capabilities and sampling optimizations to further expand the opportunities of an efficient implementation of such approach.

Defect reduction of high-density full-field patterns in jet and flash imprint lithography

Imprint lithography has been shown to be an effective technique for replication of nano-scale features. Jet and Flash Imprint Lithography (J-FIL) involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed leaving a patterned resist on the substrate. Acceptance of imprint lithography for manufacturing will require demonstration that it can attain defect levels commensurate with the defect specifications of high end memory devices. Typical defectivity targets are on the order of 0.10/cm2. This work summarizes the results of defect inspections focusing on two key defect types; random non-fill defects occurring during the resist filling process and repeater defects caused by interactions with particles on the substrate. Non-fill defectivity must always be considered within the context of process throughput. The key limiting throughput step in an imprint process is resist filling time. As a result, it is critical to characterize the filling process by measuring non-fill defectivity as a function of fill time. Repeater defects typically have two main sources; mask defects and particle related defects. Previous studies have indicated that soft particles tend to cause non-repeating defects. Hard particles, on the other hand, can cause either resist plugging or mask damage. In this work, an Imprio 500 twenty wafer per hour (wph) development tool was used to study both defect types. By carefully controlling the volume of inkjetted resist, optimizing the drop pattern and controlling the resist fluid front during spreading, fill times of 1.5 seconds were achieved with non-fill defect levels of approximately 1.2/cm2. Longevity runs were used to study repeater defects and a nickel contamination was identified as the key source of particle induced repeater defects.

Optimization of pitch-split double patterning phoresist for applications at the 16nm node

Pitch-split resist materials have been developed for the fabrication of sub-74 nm pitch semiconductor devices. A thermal cure method is used to enable patterning of a second layer of resist over the initially formed layer. Process window, critical dimension uniformity, defectivity and integration with fabricator applications have been explored. A tone inversion process has been developed to enable the application of pitch split to dark field applications in addition to standard bright field applications.

Inspection of imprint lithography patterns for semiconductor and patterned media

Imprint lithography has been shown to be an effective technique for replication of nano-scale features. Acceptance of imprint lithography for manufacturing will require demonstration that it can attain defect levels commensurate with the requirements of cost-effective device production. This work summarizes the results of defect inspections of semiconductor masks, wafers and hard disks patterned using Jet and Flash Imprint Lithography (J-FILTM). Inspections were performed with optical and e-beam based automated inspection tools. For the semiconductor market, a test mask was designed which included dense features (with half pitches ranging between 32 nm and 48 nm) containing an extensive array of programmed defects. For this work, both e-beam inspection and optical inspection were used to detect both random defects and the programmed defects. Analytical SEMs were then used to review the defects detected by the inspection. Defect trends over the course of many wafers were observed with another test mask using a KLA-T 2132 optical inspection tool. The primary source of defects over 2000 imprints were particle related. For the hard drive market, it is important to understand the defectivity of both the template and the imprinted disk. This work presents a methodology for automated pattern inspection and defect classification for imprint-patterned media. Candela CS20 and 6120 tools from KLA-Tencor map the optical properties of the disk surface, producing highresolution grayscale images of surface reflectivity, scattered light, phase shift, etc. Defects that have been identified in this manner are further characterized according to the morphology

DSA patterning options for logics and memory applications

The progress of three potential DSA applications, i.e. fin formation, via shrink, and pillars, were reviewed in this paper. For fin application, in addition to pattern quality, other important considerations such as customization and design flexibility were discussed. An electrical viachain study verified the DSA rectification effect on CD distribution by showing a tighter current distribution compared to that derived from the guiding pattern direct transfer without using DSA. Finally, a structural demonstration of pillar formation highlights the importance of pattern transfer in retaining both the CD and local CDU improvement from DSA. The learning from these three case studies can provide perspectives that may not have been considered thoroughly in the past. By including more important elements during DSA process development, the DSA maturity can be further advanced and move DSA closer to HVM adoption.

DSA via hole shrink for advanced node applications

Directed self-assembly (DSA) of block copolymers (BCPs) has become a promising patterning technique for 7nm node hole shrink process due to its material-controlled CD uniformity and process simplicity.[1] For such application, cylinder-forming BCP system has been extensively investigated compared to its counterpart, lamella-forming system, mainly because cylindrical BCPs will form multiple vias in non-circular guiding patterns (GPs), which is considered to be closer to technological needs.[2-5] This technological need to generate multiple DSA domains in a bar-shape GP originated from the resolution limit of lithography, i.e. those vias placed too close to each other will merge and short the circuit. In practice, multiple patterning and self-aligned via (SAV) processes have been implemented in semiconductor manufacturing to address this resolution issue.[6] The former approach separates one pattern layer with unresolvable dense features into several layers with resolvable features, while the latter approach simply utilizes the superposition of via bars and the pre-defined metal trench patterns in a thin hard mask layer to resolve individual vias, as illustrated in Fig 1 (upper). With proper design, using DSA to generate via bars with the SAV process could provide another approach to address the resolution issue.

Optimization of pitch-split double patterning photoresist for applications at the 16nm node

Pitch-split resist materials have been developed for the fabrication of sub-74 nm pitch semiconductor devices. A thermal cure method is used to enable patterning of a second layer of resist over the initially formed layer. Process window, critical dimension uniformity, defectivity and integration with fabricator applications have been explored. A tone inversion process has been developed to enable the application of pitch split to dark field applications in addition to standard bright field applications.

Simultaneous overlay and CD measurement for double patterning: scatterometry and RCWA approach

As optical lithography advances to 32 nm technology node and beyond, double patterning technology (DPT) has emerged as an attractive solution to circumvent the fundamental optical limitations. DPT poses unique demands on critical dimension (CD) uniformity and overlay control, making the tolerance decrease much faster than the rate at which critical dimension shrinks. This, in turn, makes metrology even more challenging. In the past, multi-pad diffractionbased overlay (DBO) using empirical approach has been shown to be an effective approach to measure overlay error associated with double patterning [1]. In this method, registration errors for double patterning were extracted from specially designed diffraction targets (three or four pads for each direction); CD variation is assumed negligible within each group of adjacent pads and not addressed in the measurement. In another paper, encouraging results were reported with a first attempt at simultaneously extracting overlay and CD parameters using scatterometry [2]. In this work, we apply scatterometry with a rigorous coupled wave analysis (RCWA) approach to characterize two double-patterning processes: litho-etch-litho-etch (LELE) and litho-freeze-litho-etch (LFLE). The advantage of performing rigorous modeling is to reduce the number of pads within each measurement target, thus reducing space requirement and improving throughput, and simultaneously extract CD and overlay information. This method measures overlay errors and CDs by fitting the optical signals with spectra calculated from a model of the targets. Good correlation is obtained between the results from this method and that of several reference techniques, including empirical multi-pad DBO, CD-SEM, and IBO. We also perform total measurement uncertainty (TMU) analysis to evaluate the overall performance. We demonstrate that scatterometry provides a promising solution to meet the challenging overlay metrology requirement in DPT.

Fundamental study of extreme UV resist line edge roughness: Characterization, experiment, and modeling

Mitigation of line edge roughness (LER) remains a significant practical issue for extreme ultraviolet (EUV) resist performance at 22 nm dimensions and below. The authors have applied a suite of experimental characterization techniques and simulation methods to a set of model EUV resists with the aim of strengthening fundamental understanding of the nature and origins of LER. The influence of resist film composition on LER has been evaluated for positive-tone chemically amplified polymer and NORIA molecular glass resists, and has been correlated the effects with surface roughness on resist films exposed at doses comparable to those at the image line edge. The effect of developer type on LER has been characterized using two distinct developer compositions that provide aqueous base positive-tone and organic solvent negative-tone processes. The time evolution of image roughness during pattern development has been visualized using interrupted development in a flow cell configuration that halts the dissolution ...

Polymer brush as adhesion promoter for EUV patterning

Current EUV lithography pushes photoresist thickness reduction to sub-30 nm in order to meet resolution targets and mitigate pattern collapse. In order to maintain the etch budgets in hard mask open, the adhesion layer in between resist and hard mask has to scale accordingly. We have reported a grafted polymer brush adhesion layer used in an ultrathin EUV patterning stack and demonstrated sub-36 nm pitch features with significant improvement over existing adhesion promotion techniques [1]. This paper provides further understanding of this class of materials from a fundamental point of view. We first propose a hypothesis of the adhesion mechanism, and probe key factors that could affect adhesion performance. The grafting kinetics study of polymer brush that contains different functional groups to the substrate shows grafting chemistry, time, and temperature are key factors that affect the printing performance. We then conduct a systematic study to understand printing capability at various pitches for different silicon-based substrates. By comparing the process window, we gain comprehensive understanding of the printing limits and failing modes with this approach. We provide a comparative study of a grafted adhesion layer vs. a conventional spin on BARC type material, including defectivity. Pattern transfer to hard mask with varied etch chemistry is conducted to understand the performance of polymer brush during etch.