Indira Seshadri

EUV patterning successes and frontiers

The feature scaling and patterning control required for the 7nm node has introduced EUV as a candidate lithography technology for enablement. To be established as a front-up lithography solution for those requirements, all the associated aspects with yielding a technology are also in the process of being demonstrated, such as defectivity process window through patterning transfer and electrical yield. This paper will review the current status of those metrics for 7nm at IBM, but also focus on the challenges therein as the industry begins to look beyond 7nm. To address these challenges, some of the fundamental process aspects of holistic EUV patterning are explored and characterized. This includes detailing the contrast entitlement enabled by EUV, and subsequently characterizing state-of-the-art resist printing limits to realize that entitlement. Because of the small features being considered, the limits of film thinness need to be characterized, both for the resist and underlying SiARC or inorganic hardmask, and the subsequent defectivity, both of the native films and after pattern transfer. Also, as we prepare for the next node, multipatterning techniques will be validated in light of the above, in a way that employs the enabling aspects of EUV as well. This will thus demonstrate EUV not just as a technology that can print small features, but one where all aspects of the patterning are understood and enabling of a manufacturing-worthy technology.

Study of alternate hardmasks for extreme ultraviolet patterning

Traditional patterning stacks for deep ultraviolet patterning have been based on a trilayer scheme with an organic planarizing layer, silicon antireflective coating or organic bottom antireflective coating, and photoresist. At an extreme ultraviolet (EUV) wavelength, there is no longer a need for reflectivity control. This offers an opportunity to look at different types of underlayers for patterning at sub-36 nm pitch length scales. An alternate hardmask can be used to develop a low aspect ratio patterning stack that can enable a larger process window at sub-36 nm pitch resolution. The hardmask layer under the resist has the potential for secondary electron generation at the resist/hardmask interface to improve resist sensitivity. This work explores EUV patterning on deposited hardmasks of various types such as silicon oxides and metal hardmasks. It also details the challenges of patterning directly on an alternate underlayer and approaches for improving patterning performance on such layers.

DSA patterning options for logics and memory applications

The progress of three potential DSA applications, i.e. fin formation, via shrink, and pillars, were reviewed in this paper. For fin application, in addition to pattern quality, other important considerations such as customization and design flexibility were discussed. An electrical viachain study verified the DSA rectification effect on CD distribution by showing a tighter current distribution compared to that derived from the guiding pattern direct transfer without using DSA. Finally, a structural demonstration of pillar formation highlights the importance of pattern transfer in retaining both the CD and local CDU improvement from DSA. The learning from these three case studies can provide perspectives that may not have been considered thoroughly in the past. By including more important elements during DSA process development, the DSA maturity can be further advanced and move DSA closer to HVM adoption.

Polymer brush as adhesion promoter for EUV patterning

Current EUV lithography pushes photoresist thickness reduction to sub-30 nm in order to meet resolution targets and mitigate pattern collapse. In order to maintain the etch budgets in hard mask open, the adhesion layer in between resist and hard mask has to scale accordingly. We have reported a grafted polymer brush adhesion layer used in an ultrathin EUV patterning stack and demonstrated sub-36 nm pitch features with significant improvement over existing adhesion promotion techniques [1]. This paper provides further understanding of this class of materials from a fundamental point of view. We first propose a hypothesis of the adhesion mechanism, and probe key factors that could affect adhesion performance. The grafting kinetics study of polymer brush that contains different functional groups to the substrate shows grafting chemistry, time, and temperature are key factors that affect the printing performance. We then conduct a systematic study to understand printing capability at various pitches for different silicon-based substrates. By comparing the process window, we gain comprehensive understanding of the printing limits and failing modes with this approach. We provide a comparative study of a grafted adhesion layer vs. a conventional spin on BARC type material, including defectivity. Pattern transfer to hard mask with varied etch chemistry is conducted to understand the performance of polymer brush during etch.

Reliable airgap BEOL technology in advanced 48 nm pitch copper/ULK interconnects for substantial power and performance benefits

This paper demonstrates the first reliable and low cost airgap BEOL technology, generated at extremely tight dimensions (48 nm pitch) in Cu/ULK. This provides 20% nested-line capacitance reduction relative to the ungapped Cu/ULK baseline. This result is of critical importance, as it validates that airgaps can be extended down to ultrafine wire levels, such as for the 10 nm technology node. Current technologies implement airgaps only at fat-wire levels; however, a significant enhancement in chip performance can be gained by including airgaps in the finest wiring levels as well. To achieve this, we benefitted from several elements which address various process, integration, and reliability challenges associated with airgap formation at such small dimensions. We present data and explanations of these solutions, and their impacts on yield, performance, defectivity and reliability (EM and TDDB).

Development of TiO2 containing hardmasks through PEALD deposition

With the increasing prevalence of complex device integration schemes, tri layer patterning with a solvent strippable hardmask can have a variety of applications. Spin-on metal hardmasks have been the key enabler for selective removal through wet strip when active areas need to be protected from dry etch damage. As spin-on metal hardmasks require a dedicated track to prevent metal contamination, and are limited in their ability to scale down thickness without comprising on defectivity, there has been a need for a deposited hardmask solution. Modulation of film composition through deposition conditions enables a method to create TiO2 films with wet etch tunability. This paper presents a systematic study on development and characterization of PEALD deposited TiO2-based hardmasks for patterning applications. We demonstrate lithographic process window, pattern profile, and defectivity evaluation for a tri layer scheme patterned with PEALD based TiO2 hardmask and its performance under dry and wet strip conditions. Comparable structural and electrical performance is shown for a deposited vs a spin-on metal hardmask.

Comprehensive analysis of line-edge and line-width roughness for EUV lithography

Pattern transfer fidelity is always a major challenge for any lithography process and needs continuous improvement. Lithographic processes in semiconductor industry are primarily driven by optical imaging on photosensitive polymeric material (resists). Quality of pattern transfer can be assessed by quantifying multiple parameters such as, feature size uniformity (CD), placement, roughness, sidewall angles etc. Roughness in features primarily corresponds to variation of line edge or line width and has gained considerable significance, particularly due to shrinking feature sizes and variations of features in the same order. This has caused downstream processes (Etch (RIE), Chemical Mechanical Polish (CMP) etc.) to reconsider respective tolerance levels. A very important aspect of this work is relevance of roughness metrology from pattern formation at resist to subsequent processes, particularly electrical validity. A major drawback of current LER/LWR metric (sigma) is its lack of relevance across multiple downstream processes which effects material selection at various unit processes. In this work we present a comprehensive assessment of Line Edge and Line Width Roughness at multiple lithographic transfer processes. To simulate effect of roughness a pattern was designed with periodic jogs on the edges of lines with varying amplitudes and frequencies. There are numerous methodologies proposed to analyze roughness and in this work we apply them to programmed roughness structures to assess each technique’s sensitivity. This work also aims to identify a relevant methodology to quantify roughness with relevance across downstream processes.

An OCD perspective of line edge and line width roughness metrology

Metrology of nanoscale patterns poses multiple challenges that range from measurement noise, metrology errors, probe size etc. Optical Metrology has gained a lot of significance in the semiconductor industry due to its fast turn around and reliable accuracy, particularly to monitor in-line process variations. Apart from monitoring critical dimension, thickness of films, there are multiple parameters that can be extracted from Optical Metrology models3. Sidewall angles, material compositions etc., can also be modeled to acceptable accuracy. Line edge and Line Width roughness are much sought of metrology following critical dimension and its uniformity, although there has not been much development in them with optical metrology. Scanning Electron Microscopy is still used as a standard metrology technique for assessment of Line Edge and Line Width roughness. In this work we present an assessment of Optical Metrology and its ability to model roughness from a set of structures with intentional jogs to simulate both Line edge and Line width roughness at multiple amplitudes and frequencies. We also present multiple models to represent roughness and extract relevant parameters from Optical metrology. Another critical aspect of optical metrology setup is correlation of measurement to a complementary technique to calibrate models. In this work, we also present comparison of roughness parameters extracted and measured with variation of image processing conditions on a commercially available CD-SEM tool.

Development of TiO2 containing hardmasks through plasma-enhanced atomic layer deposition

Abstract. With the increasing prevalence of complex device integration schemes, trilayer patterning with a solvent strippable hardmask can have a variety of applications. Spin-on metal hardmasks have been the key enabler for selective removal through wet strip when active areas need to be protected from dry etch damage. As spin-on metal hardmasks require a dedicated track to prevent metal contamination and are limited in their ability to scale down thickness without compromising on defectivity, there has been a need for a deposited hardmask solution. Modulation of film composition through deposition conditions enables a method to create TiO2 films with wet etch tunability. This paper presents a systematic study on development and characterization of plasma-enhanced atomic layer deposited (PEALD) TiO2-based hardmasks for patterning applications. We demonstrate lithographic process window, pattern profile, and defectivity evaluation for a trilayer scheme patterned with PEALD-based TiO2 hardmask and its performance under dry and wet strip conditions. Comparable structural and electrical performance is shown for a deposited versus a spin-on metal hardmask.

Development of amorphous silicon based EUV hardmasks through physical vapor deposition

Extending extreme ultraviolet (EUV) single exposure patterning to its limits requires more than photoresist development. The hardmask film is a key contributor in the patterning stack that offers opportunities to enhance lithographic process window, increase pattern transfer efficiency, and decrease defectivity when utilizing very thin film stacks. This paper introduces the development of amorphous silicon (a-Si) deposited through physical vapor deposited (PVD) as an alternative to a silicon ARC (SiARC) or silicon-oxide-type EUV hardmasks in a typical trilayer patterning scheme. PVD offers benefits such as lower deposition temperature, and higher purity, compared to conventional chemical vapor deposition (CVD) techniques. In this work, sub-36nm pitch line-space features were resolved with a positive-tone organic chemically-amplified resist directly patterned on PVD a-Si, without an adhesion promotion layer and without pattern collapse. Pattern transfer into the underlying hardmask stack was demonstrated, allowing an evaluation of patterning metrics related to resolution, pattern transfer fidelity, and film defectivity for PVD a-Si compared to a conventional tri-layer patterning scheme. Etch selectivity and the scalability of PVD a-Si to reduce the aspect ratio of the patterning stack will also be discussed.