Luc Belanger

Low-cost wafer bumping

As the demand for flip-chip interconnects mounts across an increasingly large spectrum of products and technologies, several wafer-bumping proeesses have been developed to produce the small solder features required for this interconnect technology. These processes differ signicantly in complexity and commensurate cost. Recently, a new bumping process developed at IBM Research called injection-molded solder, or IMS, has shown the capability to combine low-cost attributes with high-end capabilities. The development of IMS technology was driven by the need to reduce wafer-bumping costs while simultaneously addressing the conflicting needs of increasing wafer dimensions to 300 mm, decreasing bump and pitch dimensions below 75 µm on 150-µm centers, and optimal Pb-free alloy selection and processing. This paper describes IMS technology for both standard eutectic SnPb and Pb-free wafer bumping. Existing mainstream bumping technologies are also reviewed, with a focus on the challenges of new industry requirements. Early manufacturing challenges are addressed, including solutions that demonstrated the appropriateness of IMS technology for low-cost 300-mm Pb and Pb-free wafer bumping. Early process and reliability data are also reviewed.

Underfill selection strategy for Pb-free, low-K and fine pitch organic flip chip applications

The role of underfills is expanding from preserving solder joint reliability to also protecting fragile low-k chip dielectric layers. Traditionally, solder joints required stiff and rigid underfills. Today, low-k layers require more compliant underfill properties. Further complexity comes from the migration to Pb-free solders and changes in chip carrier materials. The myriad of candidates prohibits long term reliability testing of module hardware for every available underfill. A sequential three phase selection strategy is used to characterize and systematically eliminate undesirable candidates and to identify the few favorable underfills that have a high probability of successfully meeting module reliability requirements. The process includes use of industry practices as well as internally developed characterization methods. From an initial list of 20, the selection process identified five underfills for package qualification testing

Injection molded solder technology for Pb-free wafer bumping

A new wafer bumping technology is described that is especially suited for Pb-free applications. Although capable of using standard PbSn eutectic solder, IMS (injection molded solder) has been found to be especially suited for accommodating a wide range of Pb-free alloys with equal ease. The development of IMS technology was driven by the need to reduce wafer bumping costs while simultaneously addressing the conflicting demands of increasing wafer dimensions to 300 mm and decreasing bump and pitch dimensions below 75 /spl mu/m on 150 /spl mu/m centers. The IMS wafer bumping process uses a new head assembly that melts bulk solder alloys with precisely controlled compositions and dispenses the molten solder into multiple cavities of a wafer-sized mold plate. The mold plate is CTE matched to silicon and is reusable many times, thus reducing the per wafer bumping cost. In the process, a mold plate is scanned and filled with molten solder and inspected after solidification. Thereafter, the mold plate and device wafer are aligned and adjoined in a mirror image fashion for processing through a solder reflow furnace to transfer solder to the wafer. In this paper, early manufacturing challenges and solutions are described which allow IMS to be considered as an attractive technology for 300 mm Pb-free wafer bumping. Early process feasibility data for 200 mm wafer bumping are reviewed. Economical and environmental advantages are also discussed in relation to key process characteristics, such as solder waste reduction, use of low-cost bulk alloys, and others.

C4NP - Lead Free Flip Chip Solder Bumping Manufacturing and Reliability Data

To meet future requirements for cost, size, weight and electrical performance, microelectronic packaging is moving from wire bonds to solder bumps as the preferred method of interconnection from the device to the chip carrier or card. Flip chip in package (FCiP) requires many small bumps on tight pitch whereas wafer level chip scale packaging (WLCSP) typically requires much larger solder bumps on a greater pitch. Electroplating, solder paste printing and the direct attach of preformed solder spheres are technologies commonly used in volume production for wafer bumping. Each of these techniques has limitations in scaling from fine pitch FCiP to WLCSP. Electroplating is better suited to fine pitch, whereas solder paste printing and solder sphere attachment work well for coarser pitches. C4NP (controlled collapse chip connection new process) has proven to be suitable for this entire range of solder bump pitch. C4NP is a new solder bumping technology developed by IBM and commercialized by Suss MicroTec. C4NP addresses the limitations of existing bumping technologies by enabling low-cost, fine pitch bumping using a variety of lead-free solder alloys. C4NP is a solder transfer technology where molten solder is injected into pre-fabricated and reusable glass templates (molds). The filled mold is inspected prior to solder transfer to the wafer to ensure high final yields. Filled mold and wafer are brought into close proximity and solder bumps are transferred onto the entire 300mm (or smaller) wafer in a single process step without the complexities associated with liquid flux. C4NP technology is capable of fine pitch bumping while offering the same alloy selection flexibility as solder paste printing. The simplicity of the C4NP process makes it a low cost, high yield and fast cycle time solution for both, fine-pitch FCiP as well as WLCSP bumping applications. This paper summarizes the latest manufacturing and reliability data for high-end logic device packaging using 300mm wafers bumped with C4NP. This includes initial reliability data for C4NP lead free solder bumped devices attached to organic chip carriers. Mold fill data for CSP type dimensions is included. Solder metrology data and yield information for fine pitch applications is summarized. Relevant process equipment technology and the unique requirements to run a high volume manufacturing C4NP process are reviewed. The paper also summarizes the C4NP manufacturing cost model and elaborates on the cost comparison to alternative bumping techniques. The data in this paper is provided by IBMs packaging operations at the Hudson Valley Research Park in East Fishkill, NY and Bromont, Quebec

C4NP - data for fine pitch to CSP flip chip solder bumping

To meet nature requirements for cost, size, weight and electrical performance, microelectronic packaging is moving from wire bonds to solder bumps as the preferred method of interconnection from the device to the chip carrier or card. Flip chip in package (FCiP) requires many small bumps on tight pitch whereas wafer level chip scale packaging (WLCSP) typically requires much larger solder bumps on a greater pitch. Electroplating, solder paste printing and the direct attach of preformed solder spheres are technologies commonly used in volume production. Each of these techniques has limitations in scaling from fine pitch FCiP to WLCSP. Electroplating is better suited to fine pitch, whereas solder paste printing and solder sphere attachment work well for coarser pitches. C4NP (controlled collapse chip connection new process) has proven to be suitable for this entire range of solder bump pitch. C4NP is a new solder bumping technology developed by IBM and commercialized by Suss MicroTec. C4NP addresses the limitations of existing bumping technologies by enabling low-cost, fine pitch bumping using a variety of lead-free solder alloys. C4NP is a solder transfer technology where molten solder is injected into pre-fabricated and reusable glass templates (molds). The filled mold is inspected prior to solder transfer to the wafer to ensure high final yields. Filled mold and wafer are brought into close proximity/contact and solder bumps are transferred onto the entire 300mm (or smaller) wafer in a single process step without the complexities associated with liquid flux. C4NP technology is capable of fine pitch bumping while offering the same alloy selection flexibility as solder paste printing. The simplicity of the C4NP process makes it a low cost, high yield and fast cycle time solution for both, fine-pitch FCiP as well as WLCSP bumping applications. This paper summarizes the latest manufacturing and reliability data for high-end logic device packaging using 300mm wafers bumped with C4NP. This includes reliability data for C4NP lead free solder bumped devices attached to organic chip carriers. Mold fill data for CSP type dimensions is included. Solder metrology data and yield information for fine pitch applications is summarized. Relevant process equipment technology and the unique requirements to run a high volume manufacturing C4NP process are reviewed. The paper also summarizes the C4NP manufacturing cost model and elaborates on the cost comparison to alternative bumping techniques. The data in this paper is provided by IBMs packaging operations at the Hudson Valley Research Park in East Fishkill, NY and Bromont, Quebec.

A manufacturing approach to reducing underfill voiding on large die (> 18 mm) flip chip organic laminate packaging

The rising production levels on flip chip large dies (15 to 26 mm square) and low stand off solder C4s has brought to light greater process sensitivity with respect to the formation of voids in underfills. The formation of voids is a result of flow limitations and / or moisture diffusion from the laminate during the capillary underfill dispense and cure processes. Voiding propensity depends on a number of factors, such as underfill type and multiple variables from the laminate and chip construction and designs. Another set of factors however are controllable through process, and include preparatory bakes, preheat steps, adequate temperature control during the dispense process as well as underfill dispense pattern strategy. This paper summarizes a series of experiments conducted to better understand the interplay of several of these factors and the validation of best practices through controlled experiments on the production line. The diffusion behaviour of moisture in laminates can be roughly anticipated with standard models of moisture diffusion in epoxy and offers insights to proper adjustments of preparatory thermal treatments. The data indicates that appropriate thermal treatments to, minimise the possibility of moisture absorption and a good control of dispense parameters are key elements to reducing the occurrence of voids in underfills.