David Danovitch

Injection molded solder technology for Pb-free wafer bumping

A new wafer bumping technology is described that is especially suited for Pb-free applications. Although capable of using standard PbSn eutectic solder, IMS (injection molded solder) has been found to be especially suited for accommodating a wide range of Pb-free alloys with equal ease. The development of IMS technology was driven by the need to reduce wafer bumping costs while simultaneously addressing the conflicting demands of increasing wafer dimensions to 300 mm and decreasing bump and pitch dimensions below 75 /spl mu/m on 150 /spl mu/m centers. The IMS wafer bumping process uses a new head assembly that melts bulk solder alloys with precisely controlled compositions and dispenses the molten solder into multiple cavities of a wafer-sized mold plate. The mold plate is CTE matched to silicon and is reusable many times, thus reducing the per wafer bumping cost. In the process, a mold plate is scanned and filled with molten solder and inspected after solidification. Thereafter, the mold plate and device wafer are aligned and adjoined in a mirror image fashion for processing through a solder reflow furnace to transfer solder to the wafer. In this paper, early manufacturing challenges and solutions are described which allow IMS to be considered as an attractive technology for 300 mm Pb-free wafer bumping. Early process feasibility data for 200 mm wafer bumping are reviewed. Economical and environmental advantages are also discussed in relation to key process characteristics, such as solder waste reduction, use of low-cost bulk alloys, and others.

Chip package interaction evaluation for a high performance 65nm and 45nm CMOS Technology in a stacked die package with C4 and wirebond interconnections

An evaluation of 65 nm and 45 nm CMOS technology in a stacked die package is presented. The technology uses SiCOH advanced low K and ultra low K back end of line (BEOL) for high performance. A BEOL specific test vehicle was fabricated in these technologies and both flip chip and wirebond die used in a stacked die configuration. Manufacturability evaluations for bond and assembly processes and materials were performed and reliability studies completed on assembled modules. Results will show that the technologies are reliable in this packaging configuration.

Void-Free Underfill Process With Variable Frequency Microwave for Higher Throughput in Large Flip Chip Package Application

Moisture voiding in underfill materials can cause reliability issues for the flip chip packages. The bake-out step included in the assembly process flow to avoid this problem cannot be completely efficient for some large die size packages. This is due to complex substrate circuit designs and time delays subsequent to the bake-out step. This paper proposes using the variable frequency microwave cure to eliminate the moisture voiding of flip chip large packages assembled without any bake-out step. Results showed, for a given ramp rate, a decrease in voiding formation with decreasing VFM cure temperature. It was also found that, at low final cure temperatures, the hold steps promoted the voids formation more than the ramp steps. At high final cure temperatures, both ramp and hold steps induced voids formation, growth, and coalescence. Another interesting observation was that a slower ramp rate reduced void formation even at high cure temperature. Based on the voiding evolution study done here, two optimized cure profiles were proposed, one comprising a two-step approach and another using a one-step cure with a low ramp rate of 2 °C/min. These optimized VFM profiles demonstrated good adhesion and reliability results while providing a void-free underfill process without the need for a time-consuming bake-out step.

Study of Capillary Underfill Filler Separation in Advanced Flip Chip Packages

The key role that underfill materials play in highly reliable, advanced flip chip organic packages has generated an increased focus on their behavior and structure. One such behavior relates to the observation of filler separation from the resin matrix which, to date, has been predominantly attributed to gravity or capillary flow. The phenomenon of silica filler separation is discussed in the context of fine pitch, lead-free solder joints with copper-base (pedestal or pillar) under bump metallization and large die packages. The principle mechanism driving filler separation in these structures was confirmed as a migration of the electrostatically charged filler particles away from the copper regions and towards the solder regions of the interconnect. Based on this finding, various factors that influence the surface of the interconnects or the nature and the mobility of the filler particles during the bond and assembly process were explored. It was found that the oxide states and contact angles of the interconnect surfaces do not appear to impact the degree of filler separation. Within the range explored, average filler particle size is ineffective in changing the separation behavior. On the other hand, lower filler content somewhat increases the extent of separation and is believed to be related to an increase in particle mobility. Assembly process variables with known effects on surface interactions and underfill flow were also studied, revealing no observable shift in the occurrence of filler separation. Finally, and most importantly, a reliability study was conducted to investigate the impact of this phenomenon in a very large die (23 × 23 mm2) flip chip organic package subjected to a high level of thermomechanical stress. Using extended Deep Thermal Cycling to 2000 cycles (as opposed to the standard 1000 cycle criterion), no packaging failures occurred and no signs of interconnect degradation were observed. These results are consistent with finite element modeling of the tested package, which showed that stress changes from filler separation in regions of similar dimensions to those that were experimentally observed were within the limits of model error and typical manufacturing variability.