Valerie Oberson

Low-cost wafer bumping

As the demand for flip-chip interconnects mounts across an increasingly large spectrum of products and technologies, several wafer-bumping proeesses have been developed to produce the small solder features required for this interconnect technology. These processes differ signicantly in complexity and commensurate cost. Recently, a new bumping process developed at IBM Research called injection-molded solder, or IMS, has shown the capability to combine low-cost attributes with high-end capabilities. The development of IMS technology was driven by the need to reduce wafer-bumping costs while simultaneously addressing the conflicting needs of increasing wafer dimensions to 300 mm, decreasing bump and pitch dimensions below 75 µm on 150-µm centers, and optimal Pb-free alloy selection and processing. This paper describes IMS technology for both standard eutectic SnPb and Pb-free wafer bumping. Existing mainstream bumping technologies are also reviewed, with a focus on the challenges of new industry requirements. Early manufacturing challenges are addressed, including solutions that demonstrated the appropriateness of IMS technology for low-cost 300-mm Pb and Pb-free wafer bumping. Early process and reliability data are also reviewed.

Injection molded solder technology for Pb-free wafer bumping

A new wafer bumping technology is described that is especially suited for Pb-free applications. Although capable of using standard PbSn eutectic solder, IMS (injection molded solder) has been found to be especially suited for accommodating a wide range of Pb-free alloys with equal ease. The development of IMS technology was driven by the need to reduce wafer bumping costs while simultaneously addressing the conflicting demands of increasing wafer dimensions to 300 mm and decreasing bump and pitch dimensions below 75 /spl mu/m on 150 /spl mu/m centers. The IMS wafer bumping process uses a new head assembly that melts bulk solder alloys with precisely controlled compositions and dispenses the molten solder into multiple cavities of a wafer-sized mold plate. The mold plate is CTE matched to silicon and is reusable many times, thus reducing the per wafer bumping cost. In the process, a mold plate is scanned and filled with molten solder and inspected after solidification. Thereafter, the mold plate and device wafer are aligned and adjoined in a mirror image fashion for processing through a solder reflow furnace to transfer solder to the wafer. In this paper, early manufacturing challenges and solutions are described which allow IMS to be considered as an attractive technology for 300 mm Pb-free wafer bumping. Early process feasibility data for 200 mm wafer bumping are reviewed. Economical and environmental advantages are also discussed in relation to key process characteristics, such as solder waste reduction, use of low-cost bulk alloys, and others.

C4NP technology: Manufacturability, yields and reliability

As a part of IBM movement from Pb-rich solders to Pb-free solder, a new low cost process has been developed to deposit the solder to a capture, or under bump metal (UBM) pad, with Suss MicroTech Inc as the equipment partner. The controlled collapsed chip connection new process (C4NP) has moved, over the last 2 years, from development into manufacturing for 300 mm wafers. During this transition, a great number of process improvements have resulted in high fabrication yields. Manufacturing robustness has been achieved by clearly identifying the processes which affect the C4 structural integrity. The solder composition has been optimized to improve its mechanical properties as well as low alpha emission rate requirement. Sector partitioning methodology was used to obtain root cause for various defects which then, through replication studies, were confirmed. Key process improvements in the capture pad build, mold fabrication, and mold fill tool have been accomplished as the process has matured. Thermal undercut was identified as a mechanism of Cu seed consumption when no top Cu was available on top of the Ni UBM. C4NP technology can produce yields comparable to that of electroplated C4 Bumps. Yield learning model shows a 15% defect reduction per month since the start of the C4NP program. Technology qualification for 300 mm wafers with 200um and 150 um pitch Pb-free C4 bumps has been successfully completed.

The impact of process parameters on the fracture of device structures during chip joining on organic laminates

Detailed observations of the impact of various process parameters on the fracture of brittle structures in low-k dielectric flip chips assembled on organic laminates using lead-free metallurgies are reported. Specifically, a simple model is first presented to evaluate the stresses transmitted to the chip back end of line structures which are susceptible to failure during the reflow at chip joining. These stresses are regulated by creep deformation, so that damage to the chip can be controlled by carefully engineering the creep properties of the solder joints. We introduce new experimental techniques to monitor the creep behaviour of the joints during the reflow. In particular, we describe the use of a laser interferometer technique to monitor the chip curvature with a high sampling rate (few Hz) throughout the reflow. It is shown that these measurements can be used to predict the likelihood of causing brittle fracture in the chip structures. Additionally, we present electron backscatter diffraction (EBSD) data for the microstructure of a large number of solder joints. Using a combination of these theoretical and experimental observations, we derive a complete phenomenology for brittle fractures in the chip during the reflow. The creep-limited stresses are a strong function of solder joint plastic strain rates, which in turn are a strong function of cooling rates during the reflow. Creep properties are also a strong function of the solder metallurgy: reducing the silver content in the SnAgCu alloys results in a higher propensity for creep and correspondingly lower stresses. Thermal treatments at high temperature, such as annealing, can affect the characteristics of the intermetallic compounds, resulting in different creep properties. These trends are observed as the limiting behaviour of the relatively large number of solder joints in typical flip chip packages, but due to the small size of the solder joints (approximately 100 mum in diameter), significant variability is observed from joint to joint in the interconnect array. We link this variability to the joint microstructure by showing that the size and orientation of the few grains generally forming these joints influence the risk to cause damage in the chip.

From Leaded to Lead Free Assembly and New Packaging Technology Challenges

The migration to lead free connections in the microelectronic industry has brought forth many technical challenges, especially in the packaging technology area with respect to materials and processes. The two major drivers to these challenges are the higher melting point and the thermo-mechanical behaviour (less creep than SnPb alloy) of the replacement alloy. The higher melting point drives higher reflow temperatures during the packaging assembly as well as the card assembly and this requires the use of new materials. Higher stresses in the package can result in a reliability impact for the product. The challenge of these lead free related changes is exacerbated by other trends in leading edge organic packaging such as chip low K dielectric materials, larger package and larger chip dimensions and, reduced chip bump pitch. This paper provides the reliability results obtained through various lead free organic package test matrices and qualifications. The principal failure mechanisms are presented and are explained through material properties and finite element modeling studies. Details of the package technology qualification process and results are presented.

Fluxless Chip Join Process Using Formic Acid Atmosphere in a Continuous Mass Reflow Furnace

There is an ever growing need for a fluxless chip join process to alleviate the difficulties associated with flux cleaning in small gaps and to target fluxless packaging applications such as required for advanced photonics. Moreover, a fluxless process can enable new process flows such as in-line underfill of fragile structures or a combination tack and mass reflow operations for 3D packages. This paper discusses the development of a continuous mass reflow chip join furnace using formic acid atmosphere for fluxless, flip chip organic packaging applications. A proposed reaction mechanism between formic acid and tin oxide will be discussed. This understanding provides the basis for the reflow furnace design and the associated experimentation. A description of the prototype mass reflow furnace is provided including the formic acid delivery and abatement systems. Experimental data includes the choice of temporary adhesive material and dispense pattern to hold the assembly in place prior to reflow for chip and capacitors as well as wettability data for different formic acid concentration profiles, temperature profiles and soak times. Several test vehicles were used to investigate the impact of bump metallurgy, die size and gap between the die and organic substrate on the effectiveness of formic acid to reduce tin oxide. The impact of oxygen level was found to be critical for wettability and temporary adhesive behavior - data to support very low oxygen level is presented. A cleanliness assessment was performed on samples after chip removal and includes visual inspection, SEM and EDS data as well as XPS surface study with focus on tin redeposition. Reliability data for DTC testing of modules is presented as well as cross-sections of the interconnections formed under formic acid atmosphere.

Eternal Packages: Liquid Metal Flip Chip Devices

Gallium liquid metal joints are described as an alternative to higher melting point tin-or lead-based solder joints in flip chip packages. A complete assembly process is described, including the bumping process with the electrodeposition of gallium on corrosion resistant bonding pad, a low-temperature and low bonding force chip joining process with a HCl flux, and an underfill process with a low stiffness material. An analysis of the projected reliability of Ga joints is presented, using known properties of Ga in its liquid and solid states, finite element models of flip chip modules, and preliminary experimental results on test modules. While experimental data suggest that damage to Ga joints produced in their solid state can disappear when the joints melt, adjustments to the elastic modulus of the underfill material are discussed to prevent plastic deformation and potential fatigue failure of the solid Ga joints.

Module final test open yield optimization, of high lead flip chip on large organic package, using structured problem solving approach

The Flip Chip Plastic Ball Grid Array (FCPBGA) has become the prevalent packaging solution for mainstream microprocessors and high performance Asics. Increases in device size for these applications have begun to push the limits in terms of bond and assembly by triggering new failure modes that can impact yield and reliability. The complexity of these failure modes are such that material set behaviour knowledge and statistical analysis techniques are becoming critical to rapid product set introduction in a high volume manufacturing mode.