Luca Fanori

Highly Efficient Class-C CMOS VCOs, Including a Comparison With Class-B VCOs

This paper presents two class-C CMOS VCOs with a dynamic bias of the core transistors, which maximizes the oscillation amplitude without compromising the robustness of the oscillation start-up, thereby breaking the most severe trade-off in the original class-C topology. An analysis of several different oscillators, starting with the common class-B architecture and arriving to the proposed class-C design, shows that the latter exhibits a figure-of-merit (FoM) that is closest to the ideal FoM allowed by the integration technology. The class-C VCOs have been implemented in a 90 nm CMOS process with a thick top metal layer. They are tunable between 3.4 GHz and 4.5 GHz, covering a tuning range of 28%. Drawing 5.5 mA from 1.2 V, the phase noise is lower than -152 dBc/Hz at a 20 MHz offset from a 4 GHz carrier. The resulting FoM is 191 dBc/Hz, and varies less than 1 dB across the tuning range.

Class-D CMOS Oscillators

This paper presents class-D CMOS oscillators capable of an excellent phase noise performance from a very low power supply voltage. Starting from the recognition of the time-variant nature of the class-D LC tank, accurate expressions of the oscillation frequency, oscillation amplitude, current consumption, phase noise, and figure-of-merit (FoM) have been derived. Compared with the commonly used class-B/C architectures, the optimal class-D oscillator produces less phase noise for the same power consumption, at the expense of a higher power supply pushing. A prototype of a class-D voltage-controlled oscillator (VCO) targeted for mobile applications, implemented in a standard 65-nm CMOS process, covers a 46% tuning range between 3.0 and 4.8 GHz; drawing 10 mA from 0.4 V, the phase noise at 10-MHz offset from 4.8 GHz is -143.5 dBc/Hz, for an FoM of 191 dBc/Hz with less than 1-dB variation across the tuning range. A version of the same VCO with a resonant tail filter displays a lower 1/f3 phase-noise corner and improves the FoM by 1 dB.

Capacitive Degeneration in LC-Tank Oscillator for DCO Fine-Frequency Tuning

A digitally controlled oscillator (DCO) that achieves a minimum frequency quantization step of 150 Hz without any dithering is presented. The fine digital tuning is obtained through a capacitive degeneration of a portion of the transistor switching pair used in a classical LC-tank oscillator. The new tuning circuitry does not appreciably affect the intrinsic oscillator phase noise and allows to trim the frequency with a programmable resolution for calibration and multi-standard operation. A prototype integrated in 65 nm CMOS technology exhibits a phase noise of @ 1 MHz drawing 16 mA from a supply of 1.8 V, resulting in a FoM of 183 dBc/Hz. The active area is 700 450.

A Dither-Less All Digital PLL for Cellular Transmitters

An all-digital frequency synthesizer for cellular transmitter is presented. Low phase-noise is achieved both in-band and out-of-band exploiting a 2-dimensional Vernier time-to-digital converter and a dither-less digitally controlled oscillator. These building blocks heavily rely on digital calibration techniques to precisely and efficiently implement two-point modulation and spur cancellation in the presence of implementation impairments. The presented prototype shows an in-band phase noise of -108 dBc/Hz, an out-of-band phase noise of -160 dBc/Hz @20 MHz and in-band fractional spurs below -50 dBc. These results are obtained for an output carrier of 1.8 GHz, a reference clock of 26 MHz, with a power consumption of 41.6 mW.

A dither-less all digital PLL for cellular transmitters

Frequency synthesizer for cellular transmitters demands low phase-noise both in-band and out-of-band. The first is necessary to implement wideband modulations (e.g. WCDMA), while the second to satisfy the challenging emission mask of GSM. Moreover a low level of fractional spurs must be ensured. The paper describes the first dither-less ADPLL capable to satisfy all these requirements. These results are achieved exploiting a highly linear 2-dimension Vernier TDC and a very fine frequency resolution DCO. Both building blocks heavily rely on digital calibration techniques to precisely and efficiently implement two-point modulation and spur cancellation in the presence of many implementation impairments.

A 6.7-to-9.2GHz 55nm CMOS hybrid Class-B/Class-C cellular TX VCO

The design of very-wide-band CMOS voltage-controlled oscillators (VCOs) compliant with the phase-noise specifications of cellular transmitters is non-trivial, especially considering the GSM standard, where the phase noise exhibited by the local oscillator (LO, generated by the cascade of VCO, buffers, and usually frequency dividers) should be several dB below -162dBc/Hz at 20MHz frequency offset from the carrier. As shown in [1], challenging phase-noise requirements can embrace the WCDMA transmitter as well (e.g. -166dBc/Hz at 45MHz frequency offset for WCDMA band VIII), if cheap antenna duplexers are chosen to minimize costs. In such scenarios, and particularly in the very relevant case of WCDMA transmitting at moderate power levels, the LO power efficiency is still one of the limiting factors for a long-lasting battery life, motivating the ongoing quest for VCO power optimization.

3.3GHz DCO with a frequency resolution of 150Hz for All-digital PLL

In all-digital phase-locked loops (ADPLLs), the quantization noise introduced by the frequency discretization in the digitally controlled oscillator (DCO) can affect the performance in terms of out-of-band phase noise. In particular, the additional quantization noise has to be kept significantly lower than the intrinsic oscillator phase-noise, mandating a very fine frequency resolution (e.g. less than one kHz in GSM) [1]. Typically, in LC oscillators, the digital tuning is realized using two (or more) capacitor banks for coarse and fine tuning. The first bank is used to compensate process and temperature variation and to select the channel while the second is required for the DCO modulation inside the PLL. Since the coarse tuning range can be several hundred MHz (e.g. 800MHz in GSM [1]), a frequency resolution in the range of kHz can result in unitary elements for the capacitor banks of the order of atto-Farads. Although such values can be achieved by means of capacitive divider networks [2], the sensitivity to mismatches and parasitics of these solutions limit the robustness of the design. Staszewski et al. solved this problem by introducing a dithering of the 3 less significant bits of the DCO frequency control word [1]. This approach reduces considerably the equivalent DCO frequency resolution (from 12kHz to 30Hz) but, as occurs in any ΔΣ data converter, the quantization noise is moved to higher frequencies where generally the phase-noise specifications are more challenging. Due to this problem, the frequency of dithering must be significantly increased (225MHz) to satisfy the emission mask requirements far away from the carrier [1].

A 2.5-to-3.3GHz CMOS Class-D VCO

Power consumption in LC oscillators for wireless communications is a popular research topic, where the Class-C oscillator has been proposed to improve the efficiency of the standard Class-B oscillator (most often referred to as cross-coupled differential-pair LC-tank oscillator). In this work, we introduce the Class-D oscillator to further reduce power consumption for a desired phase noise level. Class-D oscillators have been known since 1959, but their use in GHz applications had to wait for nm CMOS processes offering excellent switches with manageable parasitic capacitances. The VCO has been designed in a standard 65nm CMOS process without any thick metal layer. The LC tank, employing a single-turn four-finger 0.59nH inductor, has a Q of 10-11 at 3GHz, estimated from post-layout simulations (including PCB) fitting the measured power consumption.

A 36mW/9mW power-scalable DCO in 55nm CMOS for GSM/WCDMA frequency synthesizers

The RF front-ends of modern smart phones are becoming more complicated as newer standards are introduced (e.g. LTE). Reconfigurability can be used to reduce their size, provided that power consumption is not adversely affected. For 2G/3G transceivers, local oscillator (LO) generation requires significant area and power. Reconfigurable voltage-controlled oscillators (VCOs) are generally used to maximize the achievable tuning range to reduce their number in the presence of many supported bands. However, no VCO capable to support both WCDMA and GSM has been reported that is also competitive with the power consumption achieved using two separate oscillators. In fact, the very demanding GSM phase-noise specs require a current up to four times higher (depending on the duplexer selectivity) than that used in the WCDMA case. In the design of an LC-tank harmonic oscillator, phase noise normalized to power consumption (i.e. the figure-of-merit, FOM), reaches an optimum at the maximum oscillation amplitude compatible with the supply voltage Vdd. This condition impairs the power reconfigurability of a VCO, since there is only one value of bias current yielding the highest FOM, once tank and Vdd are chosen. On the other hand, making the tank reconfigurable invariably results in a degradation of its Q, i.e. a reduced FOM.

A Power-Scalable DCO for Multi-Standard GSM/WCDMA Frequency Synthesizers

A Digitally Controlled Oscillator (DCO) whose power consumption can be reconfigured while maintaining an almost constant phase-noise figure-of-merit (FoM). This is achieved by using either a single-switch-pair or a complementary (i.e., double-switch-pair) oscillator topology, without disturbing the optimized LC tank of the DCO. The optimal power consumption in the complementary (P-N) configuration is reduced by 75% compared to the single-switch-pair (N-only) configuration, while the FoM is kept constant. Measurements on a 55 nm CMOS 4 GHz DCO prototype show a minimum phase noise of -129.3 dBc/Hz at 2 MHz offset from the carrier in the P-N configuration, and of -134.7 dBc/Hz in the N-only configuration, with a phase noise difference very close to the 6 dB expected from theory. The current consumption is 6 mA and 24 mA, respectively, resulting in approximately the same FoM of -185 dBc/Hz.