Luca Schiano

HDLQ: A HDL environment for QCA design

Emerging technologies have attracted a substantial interest in overcoming the physical limitations of CMOS as projected at the end of the Technology Roadmap; among these technologies, quantum-dot cellular automata (QCA) relies on different and novel paradigms to implement dense, low power circuits and systems for high-performance computing. As applicable to existing technologies, a hierarchical process can be utilized to facilitate the design of QCA circuits. Tools and methodologies both at system and physical levels are required to support all design phases. This article presents an HDL model to describe QCA “devices” (also referred elsewhere in the technical literature as building blocks, i.e., majority voter, inverter, wire, crossover) and facilitate the evaluation of their design. This tool, referred to as HDLQ, allows a designer to verify the logic characteristics of a QCA system, while supporting within a design environment different operational mechanisms (such as fault injection) and the unique features of QCA (such as bidirectionality and timing/clocking partitioning). The applicability of this design environment to various memory circuits for logic and timing verification is presented in detail. Various defective conditions for kinks due to thermodynamic effects and permanent faults due to manufacturing defects are considered for injection.

Simulation-based design of modular QCA Circuits

The design of quantum-dot cellular automata (QCA) circuits and systems is still in an infancy stage; a modular technique which relies on building blocks referred to as tiles, is proposed in this paper. This approach consists of first analyzing the logic capabilities of the basic tiles (inclusive of simulation) followed by logic mapping and connecting the tiles to form the desired circuit. The 3/spl times/3 QCA grid is presented as an example of basic block. Five types of tiles can be constructed using the 3/spl times/3 grid. A logic characterization of these tiles is presented by using a coherence vector simulation engine. It is shown that the 3/spl times/3 grid is not only area efficient, but it also offers versatile logic operation. Various QCA circuits designed using the tile-based method are presented and compared with conventional gate-based design as well as the SQUARES methodology.

Tile-based QCA design using majority-like logic primitives

The design of circuits and systems in Quantum-dot Cellular Automata (QCA) is still in infancy. The basic logic primitive in QCA is the majority voter (MV), that is not a universal function; so, inverters (INV) are also required. Blocks (referred to as tiles) are utilized in this article. A tile with a combined logic function of MV and INV (MV-like function) is proposed. It is shown that the MV-like tile can be effectively used in logic design as basic primitive. Tiles based on both the fully populated (FP) and non-fully populated (NFP) grids are investigated in detail. Various arrangements in inputs and outputs are also possible among the 4 sides of a grid, thus defining different tiles. Using a coherence vector simulation engine, it is shown that the 3 × 3 grid offers versatile logic operation. Different combinational functions such as majority-like and wire crossing are obtained using these tiles. Tile-based design of different circuits is compared to gate-based and SQUARES designs.

Markov models of fault-tolerant memory systems under SEU

A single event upset (SEU) can affect the correct operation of digital systems, such as memories and processors. This paper proposes Markov based models for analyzing the reliability and availability of different fault-tolerant memory arrangements under the operational scenario of an SEU. These arrangements exploit redundancy (either duplex or triplex replication) for dynamic fault-tolerant operation as provided by arbitration (for error detection and output selection) as well as in the presence of dedicated circuitry implementing different correction/detection codes for bit-flips as errors. The primary objective is to preserve either the correctness, or the fail-safe nature of the data output of the memory system for long mission time. It is shown that a duplex memory system encoded with error control codes has a higher reliability than the triplex arrangement. Moreover, the use of a code for single error correction and double error detection (SEC-DED) improves both availability and reliability compared to an error correction code with same error detection capabilities.

Concurrent detection of power supply noise

We propose a methodology for the concurrent detection of power supply noise affecting a general synchronous system and exceeding a tolerance bound to be chosen according to the systems constraints. Our solution is based on a suitable self-checking scheme which concurrently monitors a signal of the system clock distribution network and which is, by design, able to provide an output error message upon the occurrence of power supply noise. The produced error indication can then be exploited to recover from the detected noise (thus guaranteeing systems correct operation), or to accomplish diagnosis. Our scheme negligibly impacts systems performance, features self-checking ability with respect to a wide set of possible internal faults and keeps on revealing concurrently the occurrence of power supply noise, despite the possible presence of noise affecting also ground.

Error-resilient test data compression using Tunstall codes

This paper presents a novel technique for achieving error-resilience to bit-flips in compressed test data streams. Error-resilience is related to the capability of a test data stream (or sequence) to tolerate bit-flips which may occur in an automatic test equipment (ATE), either in the electronics components of the loadboard or in the high speed serial communication links between the user interface workstation and the head. Initially, it is shown that errors caused by bit-flips can seriously degrade test quality (as measured by the coverage), as such degradation is very significant for variable codeword techniques such as Huffman coding. To address this issue a variable-to-constant compression technique (namely Tunstall coding) is proposed. Using Tunstall coding and bit-padding to preserve vector boundaries, an error-resilient compression technique is proposed. This technique requires a simple algorithm for compression and its hardware for decompression is very small, while achieving a much higher error-resilience against bit-flips compared with previous techniques (albeit at a small reduction in compression). Simulation results on benchmark circuits are provided to substantiate the validity of this approach in an ATE environment.

Measuring the timing jitter of ATE in the frequency domain

The objective of this paper is to provide a framework by which jitter, in the output signals of a test-head board in an automatic test equipment (ATE), can be measured. In this paper, jitter phenomena caused by radiated electromagnetic interference (EMI) noise are considered. EMI noise is mainly present in the test head of an ATE as result of the activity of the dc-dc converters. An analysis has been pursued to establish the areas of the test-head board that are most sensitive to EMI noise. The most sensitive part of the test-head board has been found to occur in the loop filter of the phase-locked loop (PLL) that is used to obtain a high-frequency clock for the timing generator (TG). Different H-fields are then externally applied to the loop filter to verify the behavior of the output signal in terms of rms jitter. A frequency-domain methodology has been employed for the rms-jitter measurements. The rms-jitter variation for the radiated EMI magnitude and frequency has been characterized. Also, the orientation of the external H-field source has been investigated with respect to the target board and its effects on the measured rms jitter. For measuring the jitter, an interface circuitry has been designed on an adapter board to circumvent ground noise and connectivity problems arising from the test-head environment.

Evaluation of Error-Resilience for Reliable Compression of Test Data

This paper addresses error-resilience as the capability to tolerate bit-flips in a compressed test data stream (which is transferred from an automatic test equipment (ATE) to the device-under-test (DUT)). In an ATE, bit-flips may occur in either the electronics components of the loadboard, or the high speed serial communication links (between the user interface workstation and the head). It is shown that errors caused by bit-flips can seriously degrade the test quality (as measured by coverage) of the compressed data streams. The effects of bit-flips on compression are analyzed and various test data compression techniques are evaluated. It is shown that for benchmark circuits, coverage of test sets can be reduced by 10%-30%.

Analysis and measurement of timing jitter induced by radiated EMI noise in automatic test equipment

This paper deals with the generation, measurement and modeling of the jitter encountered in the signals of a testhead board for automatic test equipment (ATE). A novel model is proposed for the jitter; this model takes into account the radiated electromagnetic interference (EMI) noise in the head of an ATE. The RMS value of the jitter is measured at the output signal of the testhead board to validate the proposed model. For measuring the RMS value, a novel circuitry has been designed on a daughter board to circumvent ground noise and connectivity problems arising from the head environment. An H-field is applied externally at the loop filter of a phase-locked loop (PLL), thus permitting the measurement of the RMS jitter to verify the transfer function between radiated EMI and jitter variation. The error between measured and predicted jitters is within a 15% level at both 200 kHz and 500 kHz.

Self-Checking Scheme for the On-Line Testing of Power Supply Noise

We propose a self-checking scheme for the on-line testing of power supply noise, exceeding a tolerance bound, to be chosen according to system constraints. Upon the occurrence of such a noise, our scheme provides an output error message, which can be exploited for diagnostic purposes or to recover from the detected noise (thus guaranteeing correct system operation). As far as we are aware, no on-line testing scheme for power supply noise has been proposed up to now. Our scheme has negligible impact upon system performance, features a self-checking ability (with respect to a wide set of possible internal faults) and reveals, on-line, the occurrence of power supply noise, despite the possible presence of noise affecting ground.