Sarah N. McGowan

Line-edge roughness in 193-nm resists: lithographic aspects and etch transfer

We describe methods to determine transfer functions for line edge roughness (LER) from the photoresist pattern through the etch process into the underlying substrate. Both image fading techniques and more conventional focus-exposure matrix methods may be employed to determine the dependence of photoresist LER on the image-log-slope (ILS) or resist-edge-log-slope (RELS) of the aerial image. Post-etch LER measurements in polysilicon are similarly correlated to the ILS used to pattern the resist. From these two relationships, a transfer function may be derived to quantify the magnitude of LER that transfers into the polysilicon underlayer from the photoresist.1 A second transfer function may be derived from power spectral density (PSD) analysis of LER. This approach is desirable based on observations of pronounced etch smoothing of roughness in specific spatial frequency ranges. Smoothing functions and signal averaging of large numbers of line edges are required to partially compensate for large uncertainties in fast-Fourier transform derived PSDs of single line edges. An alternative and promising approach is to derive transfer functions from PSDs estimated using autoregressive algorithms.

A novel approach for the patterning and high-volume production of sub-40-nm gates

A novel approach for the patterning and manufacturing of sub-40-nm gate structures is presented. Rather than using resist or an inorganic hardmask as the patterning layer, this gate patterning scheme uses an amorphous carbon (a:C) and cap hardmask to pattern small gates. Healthy and manufacturable gate lengths have been achieved below 35 nm with this scheme, and the potential exists for further extendibility.

Defining a physically accurate laser bandwidth input for optical proximity correction (OPC) and modeling

In this study, we discuss modeling finite laser bandwidth for application to optical proximity modeling and correction. We discuss the accuracy of commonly-used approximations to the laser spectrum shape, namely the modified Lorentzian and Gaussian forms compared to using measurement-derived laser fingerprints. In this work, we show that the use of the common analytic functions can induce edge placement errors of several nanometers compared to the measured data and therefore do not offer significant improvement compared to the monochromatic assumption. On the other hand, the highlyaccurate laser spectrum data can be reduced to a manageable number of samples and still result in sub 0.5nm error through pitch and focus compared to measured spectra. We have previously demonstrated that a 23-point approximation to the laser data can be generated from the spectrometry data, which results in less than 0.1nm RMS error even over varied illumination settings. We investigate the further reduction in number of spectral samples down to five points and consider the resulting accuracy and model-robustness tradeoffs. We also extend our analysis as a function of numerical aperture and illumination setting to quantify the model robustness of the physical approximations. Given that adding information about the laser spectrum would primarily impact the model-generation run-times and not the run-times for the OPC implementation, these techniques should be straightforward to integrate with current full-chip OPC flows. Finally, we compare the relative performance of a monochromatic model, a 5-point laser-spectral fingerprint, and two Modified Lorentzian fits in a commercial OPC simulator for a 32nm logic lithography process. The model performance is compared at nominal process settings as well as through dose, focus and mask bias. Our conclusions point to the direction for integration of this approach within the framework of existing EDA tools and flows for OPC model generation and process-variability verification.

Methods and factors to optimize OPC run-time

With the increasing complexity of design and the shrinking of technology nodes, optical proximity correction has become an integral part of IC fabrication. Pattern fidelity is the baseline for any accurate OPC model. Calibrated process models are used to make iterative pattern adjustments over a fragmented design to align simulated images and the target layout. More and more advanced modeling techniques are deployed for accurate prediction of complicated 1D and 2D structures. As such, more aggressive layout situations must be taken into consideration for different process and OPC aspects such as optimization of process window, contrast, MEEF, OPC convergence, and many more. However along with different process optimizations, the mask complexity increases and the OPC run-time is also adversely affected. Often, it has been noticed that the OPC model accuracy is restricted by long OPC run-times. The variation in OPC runtime could be due to many factors, including number of finitely sized segments, multiple iterations of edge movements & simulations, convergence, multiple process conditions, step size, sitelength, model complexity, etc. Integration of fast and accurate analysis is needed to address the growing complexity of OPC solutions. We present here different approaches for OPC run-time improvement. A methodology is prepared to investigate accurate OPC models with fast runtimes. Additionally, proper selection of fragmentation, simulation sitelength, and number of iterations can be modified to achieve significant improvement in computation speed. The variation in run-time is assessed for different approaches listed above with an emphasis on OPC accuracy. Statistical analysis is used to measure image parameters and edge placement errors (EPE) for various experiments and the output is the measurement and plotting of accuracy versus run-time. This paper will present those results and suggest best practices for OPC run-time improvement that can be incorporated as a part of an OPC model building and OPC qualification flow.

OPC hotspot identification challenges: ORC vs. PWQ on wafer

The identification of OPC induced litho hotspots within the product design is essential and a must to make sure that a new OPC model is working correctly and does no harm to the design and future product. Several techniques and methods for OPC verification and identification of hotspots are known and long adopted within the field. An optical rule check done by the simulation software after OPC is one way of identifying hotspots within the design of the whole chip. This is typically done by using a DRC-type width or space check on simulation contours (nominal exposure contour or process window contours). However, the pass/fail nature of this check at a single CD value requires good calibration of the simulation model to avoid false positives and ease of disposition at tapeout. Another method is the process window qualification method which uses the defect inspection of a focus exposure matrix wafer for OPC hotspot identification. However, this can not be done prior to ordering a mask. Based on a 45nm line space layer OPC qualification, we will demonstrate how optical rule check and process window qualification is performed, what the individual results will be, and how they can be used for OPC quality evaluation. The general goal of this work is to show the capabilities of optical rule check and process window qualification, compare both methods, and detect limitations.

Minimizing poly end cap pull back by application of DFM and advanced etch approaches for 65nm and 45 nm technologies

As feature sizes decrease and the overall design shrinks, it is becoming increasingly difficult to reliably pattern gate line ends, or poly end caps, so that they are able to extend over to the field area without bridging into an adjacent feature. Furthermore, the trimming of the lines during the gate etch process is necessary due to the desire to decrease the poly length. However, the line end is also trimmed while trimming the gate sidewall, often at higher rates than the sidewall itself. This investigation focuses on decreasing the poly line end pullback, defined as the tip of the gate past active, using lithography techniques and advanced etch approaches for the 65 nm and 45 nm nodes.