Jeff J. Peterson

Nucleation and growth study of atomic layer deposited HfO2 gate dielectrics resulting in improved scaling and electron mobility

HfO2 films have been grown with two atomic layer deposition (ALD) chemistries: (a) tetrakis(ethylmethylamino)hafnium (TEMAHf)+O3 and (b) HfCl4+H2O. The resulting films were studied as a function of ALD cycle number on Si(100) surfaces prepared with chemical oxide, HF last, and NH3 annealing. TEMAHf+O3 growth is independent of surface preparation, while HfCl4+H2O shows a surface dependence. Rutherford backscattering shows that HfCl4+H2O coverage per cycle is l3% of a monolayer on chemical oxide while TEMAHf+O3 coverage per cycle is 23% of a monolayer independent of surface. Low energy ion scattering, x-ray reflectivity, and x-ray photoelectron spectroscopy were used to understand film continuity, density, and chemical bonding. TEMAHf+O3 ALD shows continuous films, density >9g∕cm3, and bulk Hf–O bonding after 15 cycles [physical thickness (Tphys)=1.2±0.2nm] even on H-terminated Si(100). Conversely, on H-terminated Si(100), HfCl4+H2O requires 50 cycles (Tphys∼3nm) for continuous films and bulk Hf–O bonding. ...

Interfacial Layer-Induced Mobility Degradation in High-

Analysis of electrical and scanning transmission electron microscopy (STEM) and electron energy loss spectra (EELS) data suggests that Hf-based high-k dielectrics deposited on a SiO2 layer modifies the oxygen content of the latter resulting in reduction of the oxide energy band gap and correspondingly increasing its k value. High-k deposition on thinner SiO2 films, below 1.1 nm, may lead to the formation of a highly oxygen deficient amorphous interfacial layer adjacent to the Si substrate. This layer was identified as an important factor contributing to mobility degradation in high-k transistors.

k

Fast transient charging effects (FTCE) are found to be the source of various undesirable characteristics of high-k devices, such as V/sub th/ instability, low DC mobility and poor reliability. The intrinsic characteristics of high-k transistors free from FTCE are demonstrated using ultra-short pulsed I-V measurements, and it is found that the intrinsic mobility of high-k devices can be much higher than what has been observed in DC based measurements. The FTCE model suggests that many of DC characterization methods developed for SiO/sub 2/ devices are not sufficiently adequate for high-k devices that exhibit significant transient charging. The existence of very strong concurrent transient charging during various reliability tests also degrades the validity of test results. Finally, the implication of FTCE on the high-k implementation strategy is discussed.

Transistors

Zr-doped HfOx high-k gate dielectric films with TiN gate electrode were sputter deposited on 1 nm SiO2 or SiOxNy interface layer. Electrical properties including the equivalent oxide thickness, flat band voltage, interface state density, and the oxide charge trapped density of the MOS capacitors were investigated with respect to fabrication parameters such as Zr doping condition, post deposition annealing ambient, and type of bottom interface layer. Excellent electrical properties were obtained for films deposited at low sputtering powers. An equivalent oxide thickness of 1.7 nm was achieved for Zr-doped HfOx on a 1 nm SiO2 interface. The leakage current is four orders of magnitude lower than that of the SiO2 film. The magnitude and polarity of the flat band voltage is influenced by the high-k film deposition method, the dopant concentration, and the post deposition annealing condition. With the same SiOxNy interface layer, the Zr-doped film has a lower leakage current and a smaller interface density of states than the undoped film.

Intrinsic characteristics of high-k devices and implications of fast transient charging effects (FTCE)

Charge trapping in high-/spl kappa/ gate dielectrics affects the result of electrical characterization significantly. DC mobility degradation and device threshold voltage instability and C-V and I-V hysteresis are a few examples. The charging effects in high-/spl kappa/ gate dielectric also affect the validity of conventional reliability test methodologies developed for SiO/sub 2/ devices. In this paper, we review high-/spl kappa/ materials specific phenomena that can affect the validity of constant-voltage-stress-based reliability test methods to address the direction of future reliability study on high-/spl kappa/ devices.

Sub 2 nm Thick Zirconium Doped Hafnium Oxide High-K Gate Dielectrics

We have demonstrated a uniform, robust interface for high-k deposition with significant improvements in device electrical performance compared to conventional surface preparation techniques. The interface was a thin thermal oxide that was grown and then etched back in a controlled manner to the desired thickness. Utilizing this approach, an equivalent oxide thickness (EOT) as low as 0.87 nm has been demonstrated on high-k gate stacks having improved electrical characteristics as compared to more conventionally prepared starting surfaces.

Validity of constant voltage stress based reliability assessment of high-/spl kappa/ devices

The equivalent oxide thickness (EOT) of high-k n-channel metal oxide semiconductor (NMOS) transistors was scaled using 3 methods, (i) reduction of the bottom interfacial layer (BIL) using NH 3 interface engineering, (ii) thickness reduction of the HfO 2 dielectric, and (iii) use of metal gate electrodes to minimize top interfacial growth formation and polysilicon depletion. NMOS transistors fabricated using these methods demonstrate 0.72 nm EOT using the NH 3 BIL with scaled HfO 2 /metal gates and 0.81 nm EOT using the O 3 BIL with scaled HfO 2 /metal gates. Charge pumping, mobility, and device performance results of these high-k NMOS transistors is discussed.

Experimental study of etched back thermal oxide for optimization of the Si/high-k interface

In this letter, the authors report on the material and electrical characterizations of high dielectric constant (k) oxide HfTiAlO for the next generation of complementary metal-oxide semiconductors. Crystallization temperature has been improved to 800–900°C versus that of HfO2. The substitution of Ti and Al in the HfO2 cubic structure results in an increased dielectric constant and an acceptable barrier height. The extracted dielectric constant is 36, and the band offset relative to the Si conduction band is 1.3eV. An equivalent oxide thickness of 11A and low leakage have been achieved with good interfacial properties.

Subnanometer Scaling of HfO2/Metal Electrode Gate Stacks

Transistor gate stack systems consisting of atomic layer deposited HfO2 with polycrystalline silicon or TiN gate electrodes have been characterized by analytical electron microscopy to elucidate underlying physical contributions to electrical performance differences. High-angle annular dark-field scanning transmission electron microscopy was used to determine film and interface thickness dimensions and chemical analysis depth profiling was obtained from electron energy loss spectra and energy dispersive x-ray spectra. The high-k gate dielectric film system is shown to be influenced by the choice of electrode material with the formation of an HfO2-poly-Si interface that increases the dielectric equivalent oxide thickness and may affect electron trapping characteristics.

HfTiAlO dielectric as an alternative high-k gate dielectric for the next generation of complementary metal-oxide-semiconductor devices

We report that precursor HfCl4 plays an important role in optimizing atomic-layer-deposition HfO2 bulk trapping characteristics. By systematic study, it has been observed that, under certain optimized precursor pulse time condition (450ms pulse as compared to standard 150ms), bulk trapping characteristics could be improved significantly without affecting the equivalent oxide thickness and leakage current characteristics of the devices. Slight improvement in mobility of the devices could also be obtained. Secondary-ion-mass-spectroscopy analysis shows that increase in the chlorine composition by increasing precursor pulse time could be attributed to the observed improvement. Drastic increase in pulse time (1500ms) negates the benefit.