M. Fukumoto

A practical trench isolation technology with a novel planarization process

We develop a new vertical-trench isolation method that utilizes a thin SiO2film in-between double photoresists for uniform top-resist coating and for an etch-back barrier, a poly-silicon film above active regions for an etch-back buffer and large tilt-angle boron ion implantations into the trench-sidewalls for narrow channel effect control. The Planarization with the Resist / Oxide / Resist and the Poly _Silicon (PRORPS) can isolate the whole surface of a 6 inch-diameter wafer very uniformly with a large process margin. The standard deviation of the threshold voltage of a n-channel MOS-FET (W/L= 10µm/0.8µm) over the whole wafer is 0.38 % at about 0.6 V threshold voltage. The narrow-channel-effect is controlled for FETs down to 0.5 µm channel width. The method is applied to the megabit SCC (Surrounded Capacitor Cell) DRAM developed here and the cells and the peripheral-circuits are isolated at the same time successfully.

A new isolation method with boron-implanted sidewalls for controlling narrow-width effect

A new isolation method for high packing density MOS devices has been developed. In this method the LOCOS technique is applied to wide isolation regions and the buried-oxide technique is applied to isolation regions less than 2 µm wide. No additional masks are needed in order to form SiO2film in the wide field regions because the photoresist is thicker near steps and inside the narrow trenches. For reducing the hump that appears in subthreshold current characteristics of n-channel MOSFETs, Using buried-oxide isolation, tilt-angle implantation to each of the four sidewalls is performed as a channel stop. The Sidewall channel stop can also control the narrow-channel effect.

A 16-Mbit DRAM with a relaxed sense-amplifier-pitch open-bit-line architecture

A 16-Mb dynamic RAM has been designed and fabricated using 0.5- mu m CMOS technology with double-level metallization. It uses a novel trench-type surrounding high-capacitance cell (SCC) that measures only 3.3- mu m/sup 2/ in cell size with a 63-fF storage capacitance. A novel relaxed sense-amplifier-pitch (RSAP) open-bit-line architecture used on the DRAM achieves a high-density memory cell array, while maintaining a large enough layout pitch for the sense amplifier. These concepts allow the small chip that measures 5.4*17.38 (93.85) mm/sup 2/ to be mounted in a 300-mil dual-in-line package with 65-ns RAS access time and 35-ns column address access time. >

A new half-micrometer p-channel MOSFET with efficient punchthrough stops

This paper describes design and characteristics of a new half-micrometer buried p-channel MOSFET with efficient punch-through stops. The approach for scaling down the buried p-channel MOSFETs is discussed by using two-dimensional process/device simulations and experimental results. The efficient punchthrough stops have realized high punchthrough resistance in half-micrometer dimensions without increasing the n-well concentration and extreme scaling of channel and source-drain junction depths. Moreover, this p-channel MOSFET shows the breakdown voltage to be as high as 10 V. The fabrication sequence is compatible with the conventional n-channel LDD MOSFETs.

A circuit technology for a self-refresh 16 Mb DRAM with less than 0.5 /spl mu/A/MB data-retention current

A 16M self-refresh DRAM achieving less than 0.5 /spl mu/A per megabyte data retention current has been developed. Several techniques to achieve low retention current, including a relaxed junction biasing (RTB) scheme, a plate-floating leakage-monitoring (PFM) system, and a V/sub BB/ pull-down word-line driver (PDWD) are described. An extension of data-retention time by three-fold and the refresh timer period by 30-fold over previously reported self-refresh DRAMs has been achieved. This results in a reduction of the ac refresh-current to less than 0.4 /spl mu/A per megabyte. Furthermore, the addition of a gate-received V/sub BB/ detector (GRD) reduces dc retention current to less than 0.1 /spl mu/A per megabyte. This allows a 20-megabyte RAM disk to retain data for 2.5 years when powered by a single button-shaped 190-mAh lithium battery.

Ion-implanted thin polycrystalline-silicon high-value resistors for high-density poly-load static RAM applications

An application of ion-implanted polycrystalline-silicon resistors for a 4- and 16-Mbit MOS static RAM cell is discussed. 4M and 16M static RAMs are designed with assumed minimum feature sizes of 0.5 and 0.25 µm of double-level polycrystalline-silicon process and power supply voltages of 3.0 and 1.5 V, respectively. The load current of the memory cell is kept at about 30 pA per cell, which is as low as that of state-of-the-art 64K static RAMs. LPCVD polycrystalline-silicon film of about 25-nm thickness is used to etch fine resistor patterns of 0.25 ∼ 0.5 µm feature sizes. Sheet resistances of 24 and 12 GΩ/ for 4M and 16M static RAM cells are controlled by arsenic implantation of about 4 × 1013and 3 × 1013cm-2at 10 keV, respectively. The ion-implanted polycrystalline-silicon resistors show nearly ideal linear current-voltage characteristics. Grain sizes of the polycrystalline-silicon films calculated from the current-voltage characteristics are in good agreement with those measured by transmission electromicrographs. It was shown that 4M and 16M static RAMs would be realized by combining the scaling-down of state-of-the-art 64K RAM cell of the double-level polycrystalline-silicon process and the thin ion-implanted polycrystalline-silicon resistors.

Electromigration in AlSiCu/TiN/Ti interconnects with Ti and TiN additional layers

AlSiCu/Ti(TiN)//TiN/Ti interconnect structures, which have been fabricated by depositing a Ti or TiN additional layer on the TiN/Ti barrier exposed in atmospheric ambient and then by depositing AlSiCu on the additional layer without breaking vacuum, have shown improved electromigration lifetimes. These were 1.9 and 6.5 times longer than that of the conventional AlSiCu//TiN/Ti structure, for the TiN and Ti additional layer, respectively. From an analysis of these results, it has been assumed that elongated lifetimes were caused by an enhancement of the Al(111) crystallographic orientation in the AlSiCu/TiN//TiN/Ti structure, and caused by both a reduction of the Si nodule concentration in AlSiCu due to Al–Si–Ti ternary alloy formation and Al(111) texture further enhanced by the additional Ti underlayer in the AlSiCu/Ti//TiN/Ti structure.

Fluorine distributions in a chemical vapor deposited tungsten silicide/polycrystalline silicon composite gate structure

A tungsten silicide/polycrystalline silicon composite gate structure has been fabricated in which tungsten silicide layers on polycrystalline silicon have been deposited by the low‐temperature chemical vapor deposition method (at 360 °C) using a WF6/SiH4 gas mixture. The fluorine distributions in this structure have been studied by secondary ion mass spectrometry. In samples with as‐deposited tungsten silicide, it has been confirmed clearly that almost all of the fluorine resides in the silicide layer. After high‐temperature annealing (above 950 °C), however, fluorine is found to diffuse easily into the gate SiO2 through the polycrystalline silicon, that is, the gate oxide has been changed into the fluorine‐doped oxide.

A circuit technology for high-speed battery-operated 16-Mb CMOS DRAM's

A battery-operated 16-Mb CMOS DRAM with address multiplexing has been developed by using an existing 0.5- mu m CMOS technology. It can access data in 36 ns when powered from a 1.8-V battery-source, and 20 ns at 3.3 V. However, this device requires a mere 57 mA of operating current for an 80-ns cycle time and only 5 mu A of standby current at 3.3 V. To achieve both high-speed and low-power operation, the following four circuit techniques have been developed: 1) a parallel column access redundancy (PCAR) scheme coupled with a current sensing address comparator (CSAC), 2) an N&PMOS cross-coupled read-bus-amplifier (NPCA), 3) a gate isolated sense amplifier (GISA) with low V/sub T/, and 4) a layout that minimizes the length of the signal path by employing the lead on chip (LOC) assembly technique. >

Self‐Aligned Titanium Silicided Junctions Formed by Rapid Thermal Annealing in Vacuum

Etude de nouvelles jonctions au silicium auto-alignees, fabriquees par recuit thermique rapide sous vide, en fonction de la resistance de couche, de la profondeur de la jonction, du courant de fuite et du profil des impuretes avec la profondeur