Shuming Xu

NexFET a new power device

A new generation of Power MOSFET technology has been introduced. The devices are manufactured in a standard 0.35µm CMOS production line with only few process modules being adapted for the requirements of vertical power transistors with a 2x improvement in Figure of Merit (FOM). This improvement results mainly from the reduction in Miller capacitance.

NexFET generation 2, new way to power

In this paper, an integrated NexFET power module is presented to meet requirements on next-generation, high efficiency and high current density DC-DC converters for computer applications. The new power module uses an innovative stacked-die package technology, implements low Vth power MOSFET in the low-side position, and introduces monolithically integrated components to avoid shoot-through and minimize voltage ringing at the switch node. In synchronous buck application, this power module achieves over 90% efficiency and low switch node ringing at high output current rating (25A) and high operation frequency (1MHz) under 12V input and 1.3V output condition.

Advanced Low-Voltage Power MOSFET Technology for Power Supply in Package Applications

In this paper, a high-current dc-dc power supply in package is reported with an emphasis on the design aspects of the low- and high-side power MOSFETs embedded in the power module. A new NexFET structure with its source electrode on the bottom side of the die (source down) is designed to enable an innovative stacked-die PSiP technology with significantly reduced parasitic inductance and package footprint. A gate voltage pulldown circuitry monolithically integrated in the low-side NexFET is introduced to effectively prevent shoot-through faults even when a very low gate threshold voltage is used to reduce conduction and body diode reverse-recovery-related power losses. In addition, an asymmetric gate resistor circuitry is monolithically integrated in the high-side NexFET to minimize voltage ringing at the switch node. With all these novel device technology improvements, the new power supply in package module delivers a significant improvement in efficiency and offers an excellent solution for future high-frequency, high-current-density dc-dc converters.

Asymmetric gate resistor power MOSFET

Power converters, e.g. in a popular synchronous buck topology, need high performance power MOSFETs in order to achieve high efficiency, low voltage ringing, ESD protection and low EMI. To satisfy these requirements, an asymmetric gate resistor power MOSFET is proposed by integrating a shunt resistor with a parallel LDMOSFET-connected diode in a source down power MOSFET (NexFET). The novel MOSFET has several advantages. First, the shunt resistor is used to slow down the turn-on speed of the high-side (HS) MOSFET, resulting in small voltage ringing of the switch node and low EMI in a synchronous buck converter. Second, the integrated diode preserves a fast turn-off speed and high conversion efficiency. Third, the bulk diode of the LDMOSFET can achieve ESD protection for gate oxide.

Design considerations on low voltage synchronous power MOSFETs with monolithically integrated gate voltage pull-down circuitry

In this paper, a monolithically integrated gate voltage pull-down circuitry is presented to avoid the unintentional C·dV/dt induced turn-on. The concept of a low threshold voltage MOSFET with this integrated gate voltage pull-down circuitry is introduced as a contributing factor to the next generation high frequency DC-DC converter efficiency improvement. Design considerations on this new device and influences of critical design parameters on device/circuit performance will be fully discussed. In synchronous buck application, this integrated power module achieves more than 2% efficiency improvement over reference solution at high operation frequency (1MHz) under 19V input and 1.3V output condition.

Low voltage NexFET with record low figure of merit

A novel planar gate double-diffused MOS (DMOS) transistor is proposed for low voltage (<;10V) DC/DC converter and load switch applications. The novel MOSFET includes a heavily doped sinker layer in the JFET region and a field plate structure on the surface of the LDD region. The LDD region is fully depleted at a small drain bias, and the field plate acts as a shield electrode significantly reducing the gate to drain capacitance. The proposed MOSFET with a rating breakdown voltage of 12 V and a maximum gate voltage of 8 V demonstrates a specific on-resistance of 5.8 mΩ·mm2 and a gate to drain charge of 0.4 nC/mm2 at a gate voltage of 4.5 V. The corresponding figure of merit (FOM= RON, sp·Qgd, sp) of the power MOSFET is 2.3 mΩ·nC, which is record low in the published literature.