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Dive into the research topics where M. R. Valero is active.

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Featured researches published by M. R. Valero.


Sensors | 2015

A High Performance LIA-Based Interface for Battery Powered Sensing Devices.

D. García-Romeo; M. R. Valero; N. Medrano; B. Calvo; S. Celma

This paper proposes a battery-compatible electronic interface based on a general purpose lock-in amplifier (LIA) capable of recovering input signals up to the MHz range. The core is a novel ASIC fabricated in 1.8 V 0.18 µm CMOS technology, which contains a dual-phase analog lock-in amplifier consisting of carefully designed building blocks to allow configurability over a wide frequency range while maintaining low power consumption. It operates using square input signals. Hence, for battery-operated microcontrolled systems, where square reference and exciting signals can be generated by the embedded microcontroller, the system benefits from intrinsic advantages such as simplicity, versatility and reduction in power and size. Experimental results confirm the signal recovery capability with signal-to-noise power ratios down to −39 dB with relative errors below 0.07% up to 1 MHz. Furthermore, the system has been successfully tested measuring the response of a microcantilever-based resonant sensor, achieving similar results with better power-bandwidth trade-off compared to other LIAs based on commercial off-the-shelf (COTS) components and commercial LIA equipment.


international symposium on circuits and systems | 2012

An ultra low-power low-voltage class AB CMOS fully differential OpAmp

M. R. Valero; S. Celma; N. Medrano; B. Calvo; C. Azcona

This paper presents an ultra low-power class AB operational amplifier (OpAmp) designed in a low-cost 0.18 μm CMOS technology. Rail-to-rail input operation is achieved by using complementary input pairs with adaptive bias to enhance slew-rate. A class AB output stage is employed. For low-voltage low-power operation, the transistors both in the input and the output stage are biased in the sub-threshold region. The simulated DC open loop gain is 51 dB, the unity gain frequency is 40 kHz with a 65° phase margin and the slew-rate is 0.12 V/μs with 10 pF capacitive loads. A common-mode feed-forward circuit (CMFF) increases CMRR, keeping the DC gain almost constant: its relative error remains below 1 % for a (-40°C, +120°C) temperature range. The proposed OpAmp consumes only 1 μW at 0.8 V supply.


IEEE Transactions on Instrumentation and Measurement | 2011

CMOS Voltage-to-Frequency Converter With Temperature Drift Compensation

M. R. Valero; S. Celma; B. Calvo; N. Medrano

This paper presents a new complementary metal-oxide-semiconductor (CMOS) differential voltage-to-frequency converter (VFC) suitable for sensor signal conditioning. Designed in a low-cost 0.18- μm CMOS process, the proposed VFC consumes less than 0.4 mW at a 1.8-V supply. For a differential input range of 0-1.2 V, output frequency varies from 0.1 to 1.1 MHz with a linearity error of less than 0.4%. A new temperature compensation technique keeps the gain error below 2.4% over the whole frequency span for a range of -20°C- +120°C.


ieee sensors | 2014

A CMOS 1.2-V 1.7-mW lock-in amplifier for sensing applications up to 0.7-MHz

M. R. Valero; N. Medrano; S. Celma; B. Calvo

This paper proposes a 1.2-V 1.7-mW 0.7-MHz bandwidth dual-phase analog lock-in amplifier (LIA) for embedded sensing applications integrated in a 0.18-μm CMOS technology. Unlike to most of the reported up-to-date LIAs, which are designed to condition a specific sensor operating at a particular frequency, this work presents a general purpose low power battery-compatible LIA, so that the benefits of phase sensitive detection (PSD) techniques in sensor signal processing can be exploited in a wider spectrum of applications, such as multi-sensing devices. Additionally, a high simplicity and versatility with a good trade-off between its main performances and power has been sought. Experimental results for signals buried in white noise confirm the capability of the LIA to effectively recover information from signal-to noise power ratios up to -33 dB with errors below 2 % up to 0.7 MHz with 1.7 mW of power consumption, showing up that higher frequency operation with a reduction in voltage supply and power with respect to previously reported LIAs is achieved.


european conference on circuit theory and design | 2013

A compact low-voltage first-order temperature-compensated CMOS current reference

B. Calvo; C. Azcona; N. Medrano; S. Celma; M. R. Valero

This paper presents the design of two new low-voltage first-order temperature compensated CMOS current references. To achieve compact topologies able to operate under low voltage with low power consumption, they are based on the simplest approach of cross-coupled current mirrors, and compensation is obtained by introducing a temperature dependent current mirror ratio. Results for 0.18 μm CMOS implementations show that the proposed 1 μA references operate with supplies down to 1 V showing temperature drifts below 238 ppm/°C over the (-40 to 120°C) range, which makes them suitable for low-cost portable applications.


european conference on circuit theory and design | 2013

OpAmp design for lock-in amplifiers in portable sensing systems

M. R. Valero; S. Celma; N. Medrano; B. Calvo

This paper presents a 1.2 V low-power rail-to-rail class AB operational amplifier (OpAmp) suitable for integrated lock-in amplifiers. The proposed OpAmp has been designed in a standard 0.18 μm CMOS technology. For a 1.2 V single supply and 81 μW power consumption, simulations shows a 86 dB open loop gain, 56o phase margin, 17 MHz unity gain frequency with 1 pF load and 97 dB CMRR. Adaptive biasing provides 33 V/μs slew-rate for a 1 pF capacitive load. A compact and reliable lock-in amplifier (LIA) has been designed using the proposed circuit. Post-layout results for noisy signals confirm the capability of the LIA to effectively recover information from signal-to-noise ratios down to -26 dB with errors below 4.2% up to 50 kHz and a power consumption of only 675 μW.


european solid-state circuits conference | 2012

A 0.8-V 1.2-μW rail-to-rail fully differential OpAmp with adaptive biasing

M. R. Valero; S. Celma; N. Medrano; B. Calvo

This paper presents an ultra low-power rail-to-rail fully differential operational amplifier (OpAmp) fabricated in a standard 0.18 μm CMOS technology. The proposed circuit uses transistors biased in the sub-threshold region for low-voltage low-power operation. For a 0.8 V single supply and 8 pF loads, experimental measurements shows a 51 dB open loop gain, 62° phase margin, 57 kHz unity gain frequency and a 750 mV linear output swing. Adaptive biasing provides 0.14 V/μs slew-rate, while a 73 dB CMRR is achieved thanks to a CMFF circuit, demonstrating the correct functionality of the OpAmp with a power consumption of 1.2 μW.


Microelectronics Journal | 2015

A high-performance 1.2V-99µW rail-to-rail CMOS class AB amplifier

M. R. Valero; N. Medrano; S. Celma; B. Calvo

This paper presents a compact, reliable 1.2V low-power rail-to-rail class AB operational amplifier (OpAmp) suitable for integrated battery powered systems which require rail-to-rail input/output swing and high slew-rate while maintaining low power consumption. The OpAmp, fabricated in a standard 0.18µm CMOS technology, exhibits 86dB open loop gain and 97dB CMRR. Experimental measurements prove its correct functionality operating with 1.2V single supply, performing very competitive characteristics compared with other similar amplifiers reported in the literature. It has rail-to-rail input/output operation, 5MHz unity gain frequency and a 3.15V/µs slew-rate for a capacitive load of 100pF, with a power consumption of 99µW.


international symposium on circuits and systems | 2014

Rail-to-rail CMOS complementary input stage with alternating active differential pairs

M. R. Valero; Alejandro Roman-Loera; J. Ramirez-Angulo; N. Medrano; S. Celma

A simple and power efficient scheme for input rail-to-rail Op-Amp operation with constant gm and CMRR over the common mode input range is introduced. The input stage uses complementary differential pairs but only one pair is active at a time. Three implementations of the scheme are discussed. They use very compact control circuitry to turn only one of the differential pairs at a time. Simulations and experimental verification of the proposed scheme are provided from a test chip prototype in 0.5μm CMOS technology.


conference on ph.d. research in microelectronics and electronics | 2011

A CMOS micropower voltage-to-frequency converter for portable applications

C. Azcona; B. Calvo; N. Medrano; S. Celma; M. R. Valero

This paper presents a micropower 1.2-V 0.18-µm CMOS temperature-compensated voltage-to-frequency converter for portable applications. Results show that the proposed converter has a power consumption of 60 µW (15 nW in sleep mode) operating over a (0.0 – 1.0 V) input voltage range with two different selectable output ranges, 0 – 0.5 MHz and 0.5 – 1 MHz. It achieves a relative error below 3 %, a gain error below 3.6 % and a linearity error of 0.004 % (14 bits) over the whole frequency span.

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N. Medrano

University of Zaragoza

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S. Celma

University of Zaragoza

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B. Calvo

University of Zaragoza

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J. Ramirez-Angulo

New Mexico State University

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C. Azcona

University of Zaragoza

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Liudi Jiang

University of Southampton

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Nicholas Hale

University of Southampton

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David Moser

University Hospital Southampton NHS Foundation Trust

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