M. Taghi Ahmadi

Vertical double gate MOSFET for nanoscale device with fully depleted feature

A fully depleted vertical double gate MOSFET device was revealed with the implementation of oblique rotating implantation (ORI) method in 25 nm silicon pillar thickness. Several devices with various gate lengths (20–100 nm) were simulated and evaluated using virtual wafer tool. The implication of gate length reduction on the short channel effect (SCE) shows considerable advantages with higher current drives at lower gate length, while the low subthreshold swing could balance the threshold voltage roll‐off in the term of increasing power consumption. As a result, the drive current and also SCE controllability will be a benefit in the fully depleted device.

Influences of Sr-90 beta-ray irradiation on electrical characteristics of carbon nanoparticles

This work is concerned with the low cost fabrication of carbon nanoparticles (CNPs), and its application to beta ray detection. The structural and morphological properties of the CNPs were obtained by spectral and microscopy techniques. A system based on CNPs application in the metal-semiconductor-metal (MSM) junction platform, which acts as a beta-ray (β-ray) sensor, is fabricated. The prototype is characterised by modelling, Monte Carlo simulation, and electrical investigations. Changes to the electrical behaviour of the proposed MSM system due to β-ray irradiation are validated by experimental results in both Ohmic and non-Ohmic (Schottky) contacts. The simulation was performed using the MCNPX code, which showed that most of the β-ray energies are deposited into CNPs and electrodes. However, in the Ohmic contact, because the β-ray is induced, the current of CNPs is decreased. The reduction of the current might be due to the change of the carrier properties by increasing the scattering of electrons. The...

Ballistic saturation velocity of quasi-2D Low- dimensional nanoscale field effect transistor (FET)

The saturation velocity is found to be ballistic regardless of the device dimensions. The ballistic intrinsic velocity is based on streamlining of the randomly oriented velocity vectors in zero electric field. In the degenerate realm, the saturation velocity is shown to be the Fermi velocity that is independent of temperature but strongly dependent on carrier concentration. In the non‐degenerate realm, it’s becomes thermal velocity that depends only on the ambient temperature. The drain carrier velocity is revealed to be smaller than the saturation velocity due to finite electric field at the drain‐end. An excellent agreement is revealed when comparing the model to 80 nm fabricated MOSFET.

Analytical Study of Carrier Statistic in 2‐Dimensional Nanoscale P‐MOS

The carrier statistics for 2‐dimensional (2‐D) p‐type nanostructure was elaborated, especially for p‐MOSFET. According to the energy band diagram, the effective mass (m*) in the p‐type silicon is mostly dominated by heavy hole because of the large gap between heavy hole and light hole in k = 0. The carrier concentration in 2‐D was obtained using the calculated density of state, based on the Fermi—Dirac statistic on the order of zero (I0). In the nondegenerate regime the carrier statistic results replicate the form the Boltzmann statistics. However, the results vary in degenerate regime, which result in the presence of ηV. The results for 2‐D carrier statistic were numerically computed, and the comparison of the carrier statistic for degenerate and non‐degenerate regime is presented, along with its respective Fermi‐Dirac integral. It is also found that the density of state of hole in 2‐D p‐MOSFET is independent of the temperature.

Design and analysis of nanoscale vertical MOSFET using oblique rotating implantation (ORI) method with reduced parasitic capacitance

The design and analysis of an enhanced performance of vertical MOSFET is revealed by adopting the oblique rotating ion implantation (ORI) method combined with fillet oxidation (FILOX) technology. These CMOS compatible processes have formed the symmetrical self‐aligned source/drain regions over the silicon pillar with sharp vertical channel profiles. Accordingly, an increased numbers of electrons in the channel with decreased channel length (Lg) have shown to improved the threshold voltage, sub‐threshold swing, drive‐on current, leakage current, DIBL and drain saturation current significantly. The drain overlap capacitance is a factor of 0.2 lower and the source overlap capacitance is a factor of 1.5 lower than standard vertical MOSFETs.

Numerical analysis of vertical double gate MOSFETs (VDGM) with dielectric pocket (DP) effects on silicon pillar for nanoscale transistor

Numerical analysis of vertical double‐gate MOSFETs (VDGM) that incorporates dielectric‐pocket (DP) is addressed in this paper for the suppression of short‐channel effects (SCE) and bulk punch‐through. The comparison between standard and VDGM‐DP revealed the advantages of DP for inhibition of SCE. The transfer and output characteristics of the VDGM‐DP indicates a reasonable value of threshold voltage (VT), drive and off‐leakage current (ION and IOFF), sub‐threshold swing (S) and Drain Induced Barrier Lowering (DIBL). The DP incorporated on top of transistor turret is revealed to increase the saturation current IDsat due to drain‐end electric field reduction that improved the carrier mobility and the drain current tremendously.