M. Traving

Comprehensive study of the resistivity of copper wires with lateral dimensions of 100 nm and smaller

Copper wires were prepared in a silicon oxide matrix using the methods of semiconductor manufacturing and were electrically characterized. The width of the smallest structure was 40 nm and of the largest, 1000 nm; the heights were 50, 155, and 230 nm. Many samples of each size have been measured in order to perform a systematic investigation. The resistivity of the sample was extracted using the temperature coefficient of resistance. A significant increase in the resistivity was found for the small structures (roughly a factor 2 for 50-nm width). A model based on physical parameters was used in the analysis of the electrical data and very good agreement was obtained. The sensitivity of the various model parameters obtained by a best-fit procedure to the experimental data has been investigated. The impact of width and height on the resistivity, the influence of electron scattering at grain boundaries compared to surface scattering, and the impact of grain sizes and impurities will be discussed in detail.

Damascene and subtractive processing of narrow tungsten lines: Resistivity and size effect

Narrow W lines with linewidths down to ~40 nm were manufactured by both damascene and subtractive processing. The dependence of the resistivity on the linewidth was studied for different deposition temperatures of the W layer. Generally, the resistivity decreases for decreasing deposition temperature of W. The resistivity increases with decreasing linewidth for both processes due to size effects. However, the W damascene lines show a much steeper increase of the resistivity than etched W lines. In the case of the etched lines the grain size is already fixed after deposition of the W and, therefore, the resistivity increase is caused by an increase of the surface scattering contribution solely. In the case of the damascene lines the line geometry restricts the grain size and, therefore, with decreasing linewidth both an increase of the grain boundary scattering and of the surface scattering contributes to the resistivity. The different behavior of the resistivities can be understood within a compact model ...

Scaling of parasitics and delay times in the backend-of-line

The role of interconnects in determining the delay times of future generation integrated circuits has been studied. Two scenarios were investigated; one using ITRS values for dielectric permeability and conductor resistivity, and an alternative taking into account size effects on the resistivity and using more conservative values for k. To develop a concise model of the delays, the contributions of the individual parasitic elements and their evolution for future generations were investigated for the different scenarios. The calculations of the delays show a dramatic increase for small feature sizes. The predictions of the two models differ significantly especially for long wires, with the conservative model showing much longer delay times. These results make the introduction of a hierarchical metallization seem even more important.

Scaling of Metal Interconnects: Challenges to Functionality and Reliability

Copper‐based nano interconnects featuring CDs well beyond today’s chip generations and air gap structures were fabricated and subjected to electrical characterization and tests to get already today insight on functionality and reliability aspects of metallization schemes in future semiconductor products. Size effects observed already in today’s advanced products will definitely limit the resistivity in future interconnects. Copper diffusion barrier layers were scaled down to the 1nm regime of thicknesses without observable degradation effects regarding adhesion properties and functionality. Interconnect reliability was found to decrease with decreasing barrier thickness. Worst results regarding adhesion properties and interconnect reliability were obtained for vanishing barrier thickness which promotes unrestricted mass flow of copper along the interconnect line. Air gaps were developed and characterized as an alternative approach to porous ultra low‐k materials. They allowed the realization of effective ...