Günther Schindler

Comprehensive study of the resistivity of copper wires with lateral dimensions of 100 nm and smaller

Copper wires were prepared in a silicon oxide matrix using the methods of semiconductor manufacturing and were electrically characterized. The width of the smallest structure was 40 nm and of the largest, 1000 nm; the heights were 50, 155, and 230 nm. Many samples of each size have been measured in order to perform a systematic investigation. The resistivity of the sample was extracted using the temperature coefficient of resistance. A significant increase in the resistivity was found for the small structures (roughly a factor 2 for 50-nm width). A model based on physical parameters was used in the analysis of the electrical data and very good agreement was obtained. The sensitivity of the various model parameters obtained by a best-fit procedure to the experimental data has been investigated. The impact of width and height on the resistivity, the influence of electron scattering at grain boundaries compared to surface scattering, and the impact of grain sizes and impurities will be discussed in detail.

Electrical assessment of copper damascene interconnects down to sub-50 nm feature sizes

The feasibility of fabrication of sub-50 nm copper interconnects was demonstrated. A process flow to obtain wires with line widths far below the limits given by lithography using a removable spacer technique was developed for copper damascene lines. The behavior of the electrical resistivity of lines with feature sizes down to 43 nm was investigated for temperatures ranging from 80 to 573 K. An increase of the electrical resistivity with shrinking dimensions was observed as a result of size effects. The experimental data will be discussed in detail and can be well described by a contribution of electron surface scattering and grain-boundary scattering. The results clearly demonstrate that cooling of Cu wires will no longer help to maintain low electrical resistivity in the mesoscopic regime, i.e. when feature sizes of metal wires approach the mean free path of the charge carriers. For future technology generations size effects, which are not explicitly addressed in the ITRS, will come into play and will become a significant contributor to wire related delay times.

Lifetime estimation due to imprint failure in ferroelectric SrBi2Ta2O9 thin films

Two different failure modes for a ferroelectric memory cell caused by imprint, the read failure due to the loss of polarization, and the write failure due to the shift of the hysteresis loop are investigated. The quasistatic hysteresis loop allows us to distinguish which failure mode is dominating in a ferroelectric random access memory application and, hence, it can also be used as a powerful tool for lifetime estimation of ferroelectric thin films limited by imprint failure under operating conditions. The experimental results show that the write failure is only decisive for very low voltage operation (Vp<1.25 V), whereas for the Pt/SrBi2Ta2O9/Pt under investigation the read failure is the dominant failure mode for operating voltages exceeding 1.25 V.

Electrical characterization of copper interconnects with end-of-roadmap feature sizes

Abstract The metallization of trenches with end-of-roadmap feature sizes using a damascene approach is demonstrated. By applying an adapted spacer technique, narrow trenches were fabricated in an oxide-based intermetal dielectric, filled with barrier metal and Cu and subsequent CMP of the copper/barrier bi-layer. Thus damascene metal lines with widths down to 40 nm and aspect ratios exceeding 4 could be fabricated. These metal lines could be characterized electrically up to a length of almost 10 cm. The data show an increase of resistivity for small line widths, which can be explained by surface scattering. The surface effects can also be seen in the temperature dependence of the resistance. The maximum current density was shown to exceed those of todays interconnect lines by a factor of 2, exceeding the ITRS requirements for the maximum current density of such structures.

Damascene and subtractive processing of narrow tungsten lines: Resistivity and size effect

Narrow W lines with linewidths down to ~40 nm were manufactured by both damascene and subtractive processing. The dependence of the resistivity on the linewidth was studied for different deposition temperatures of the W layer. Generally, the resistivity decreases for decreasing deposition temperature of W. The resistivity increases with decreasing linewidth for both processes due to size effects. However, the W damascene lines show a much steeper increase of the resistivity than etched W lines. In the case of the etched lines the grain size is already fixed after deposition of the W and, therefore, the resistivity increase is caused by an increase of the surface scattering contribution solely. In the case of the damascene lines the line geometry restricts the grain size and, therefore, with decreasing linewidth both an increase of the grain boundary scattering and of the surface scattering contributes to the resistivity. The different behavior of the resistivities can be understood within a compact model ...

Scanning probe microscopy — a tool for the investigation of high-k materials

Abstract Dielectric/ferroelectric materials such as BaxSr1−xTiO3 (BST), PbZrxTi1−xO3 (PZT), and SrBi2Ta2O9 (SBT) are currently being investigated for integration into high-density CMOS technology. In this study, the micromorphology of polycrystalline BST, PZT, and SBT films was imaged by atomic force microscopy (AFM). Electrical properties such as polarization of the crystallites as well as tunneling/leakage currents were measured by electrostatic force microscopy (EFM) and conductive atomic force microscopy (C-AFM), respectively. EFM images revealed that single crystallites of PZT and SBT films could be polarized by applying a voltage of a few volts between tip and film. Time and temperature stability of the polarization were studied in annealing experiments. As expected, polarization decreased faster with increasing temperature. C-AFM on BST and SBT showed enhancement of leakage currents in grains and grain boundary regions, especially in depressions between adjacent crystallites. In thin SBT films, sites of leakage current were frequently visible at the edges of steps of test patterns. The results achieved demonstrate that scanning probe microscopy (SPM) techniques are a valuable tool for the elucidation of the microscopic properties of high-k materials. In particular, they are capable of revealing the defects and discontinuities of the films that affect capacitor performance and reliability due to, e.g., fatigue, imprint, and leakage currents, issues of key interest in product applications.

Processing technology for the investigation of sub-50 nm copper damascene interconnects

Abstract The scalability of today’s metallization in interconnect technology is demonstrated and nano-interconnects of critical dimension regarding the International Technology Roadmap for Semiconductors (ITRS) roadmap requirements for the 22 nm technology node are shown. Sub-50 nm copper damascene lines were fabricated using an adapted spacer technique with current optical lithography and standard manufacturing equipment for processing 150 or 200 mm diameter wafers. For comparison an electron beam microscope based lithography was used for direct writing of patterns with narrow pitches. For both methods particular attention will be paid to issues of patterning and adaptation of unit processes as well as metal deposition. Electrical measurements for assessing the fabricated nano-interconnects with respect to the influences of barrier and seed layer thicknesses are shown briefly. The feasibility of interconnects with end-of-roadmap feature sizes demonstrated by these measurements gives reason to expect a bright future of copper interconnect processing technology.

Review of SrBi2Ta2O9 thin films capacitor processing

Abstract Ferroelectric memories (FeRAMs) are new types of memories especially suitable for mobile applications due to their unique properties like non-volatility, small DRAM-like cell size, fast read and write as well as low voltage/low power behavior. Although standard CMOS processes can be used for frontend and backend processes, FeRAM technology development has to overcome major challenges due to new materials used for capacitor formation. This work gives an overview of SrBi2Ta2O9 (SBT) thin films capacitor processing using Pt as electrode material. The study describes in detail SBT formation using metal organic deposition (MOD) as well as influence of electrode thickness and capacitor patterning on SBT electrical properties. Also, results for integration of the capacitor process into a 0.5μm CMOS process with 2-layer tungsten/aluminum metallization as well as stacked capacitor results are given.

Low temperature process and thin SBT films for ferroelectric memory devices

Abstract At crystallization temperatures of about 800°C bismuth layered oxide SrBi2Ta2O9 (SBT) deposited by MOD develops good ferroelectric properties for use in FeRAM devices. But scaling down the film thickness of SBT below 150 nm only shorts are measured at this crystallization temperture after top electrode deposition. Working Pt/SBT/Pt-capacitors are achieved by reducing the crystallization temperature. Also temperatures of 800°C are too high for integration of the SBT module in a stacked capacitor architecture for high density memory devices. Therefore, a process is needed to reduced the crystllization temperature of SBT, called ”Low Temperature Process“. In this work the electric properties of spin-on processed SBT crystallized in a temperature window from 650°C up to 800°C are investigated. As shown by XRD, transtion of the nonferroelectric Fluorite phase to the Aurivillius phase takes place at approximately 625°C. Increasing the cystallization temperature gives better crystaallized SBT films with bigger SBT graains. However, film prosity is also increasing with temperature. Electrical results of stoichiometric variations of SBT are presented. SEM pictures show that cluster formation is correlated with less film porosity at lower temperatures.

Air gap technology by selective ozone/TEOS deposition

A technology for fabrication of air gaps is presented which is based upon selective ozone/TEOS deposition of oxide. Due to the isotropic growth direction of this process, some disadvantages of the more common approaches by nonconformal CVD processes can be avoided. It is demonstrated that air gap technology has the potential to reduce the capacitance between adjacent metal lines roughly by a factor of 2 compared to full structures without air gaps.