Peter C. S. Scholtens

A 6-b 1.6-Gsample/s flash ADC in 0.18-/spl mu/m CMOS using averaging termination

A 1.6 Gsample/s 6b flash analog-to-digital converter in 0.18 /spl mu/m CMOS is for storage read channels. The array of amplifiers and averaging resistors is terminated with less overrange while maintaining full-scale linearity. Consuming 340 mW, it achieves 5.7 effective bits at DC and 5 effective bits at 660 MHz.

Assessment of the merits of CMOS technology scaling for analog circuit design

Key device parameters such as drain current, transconductance, current factor, capacitance, etc. are linked to typical analog circuit level performance criteria, as a function of the CMOS technology node. Subsequently, speed and power implications for an analog-to-digital converter building block are estimated. Significant power efficiency improvements are predicted as a result of scaling to deep sub-micron technology nodes.

Systematic power reduction and performance analysis of mismatch limited ADC designs

This paper focuses on several methods to save power consumption in mismatch limited ADC designs, like flash and folding architectures. Migrating existing designs to a next submicron technology helps to reduce the power consumption significantly. It is shown that decreasing bandwidth and sample rate creates a more than linear reduction of the power consumption. Both of these methods are addressed in this paper. Also the balance between power consumption of the analog and digital circuitry is examined. An existing 6-bit 1.6GS/s ADC in 0.18/spl mu/m CMOS is transferred to a 0.12/spl mu/m technology. The sampling rate is reduced to 260MS/s, the measured ERBW to 124MHz while running at only 32mW. As the bandwidth is downscaled 5/spl times/, the power consumption is reduced by 10/spl times/, which results in an improved conversion efficiency. As the design topology is unaltered, the implemented design sets a reference for evaluation of any low-power technique.

Scalable high-speed analog circuit design

The impact of scaling on the analog performance of MOS circuits was studied. The solution space for analog scaling was explored between two dimensions: a “standard digital scaling” axis and an “increased bandwidth and dynamic-range” axis. Circuit simulation was applied to explore trends in noise and linearity performance under analog operating conditions at device level and for a basic circuit block. It appears that a single scaling rule is not applicable in the analog circuit domain.

A 1.6 GS/s, 16 times interleaved track & hold with 7.6 ENOB in 0.12 /spl mu/m CMOS [ADC applications]

A 1.6 GS/s track and hold circuit that produces 16 interleaving, 100 MS/s voltage buffered output signals is presented. The achieved SFDR for a 950 MHz full scale input signal is 50 dB. Phase alignment is better than 2 ps and aperture uncertainty is less than 0.8 ps (RMS). The chip includes two analog to digital converters and a switching matrix to accommodate measurement of all sampled output signals and their timing relation. Chip area is 0.14 mm/sup 2/, excluding the AD converters. The chip is made in a 0.12 /spl mu/m, 1.2 V CMOS process. Power consumption of the interleaving T/H circuit is 32 mW.