P.M. Raj

The SOP for miniaturized, mixed-signal computing, communication, and consumer systems of the next decade

From cell phones to biomedical systems, modern life is inexorably dependent on the complex convergence of technologies into stand-alone products designed to provide a complete solution in small, highly integrated systems with computing, communication, biomedical and consumer functions. The concept of system-on-package (SOP) originated in the mid-1990s at the NSF-funded Packaging Research Center at the Georgia Institute of Technology. This can be thought of as a conceptual paradigm in which the package, and not the bulky board, as the system and the package provides all the system functions in one single module, not as an assemblage of discrete components to be connected together, but as a continuous merging of various integrated thin film technologies in a small package. In the SOP concept, this is accomplished by codesign and fabrication of digital, optical, RF and sensor functions in both IC and the package, thus distinguishing between what function is accomplished best at IC level and at package level. In this paradigm, ICs are viewed as being best for transistor density while the package is viewed as being best for RF, optical and certain digital-function integration. The SOP concept is demonstrated for a conceptual broad-band system called an intelligent network communicator (INC). Its testbed acts as both a leading-edge research and teaching platform in which students, faculty, research scientists, and member companies evaluate the validity of SOP technology from design to fabrication to integration, test, cost and reliability. The testbed explores optical bit stream switching up to 100 GHz, digital signals up to 5-20 GHz, decoupling capacitor integration concepts to reduce simultaneous switching noise of power beyond 100 W/chip, design, modeling and fabrication of embedded components for RF, microwave, and millimeter wave applications up to 60 GHz. This article reviews a number of SOP technologies which have been developed and integrated into SOP test bed. These are: 1) convergent SOP-based INC system design and architecture, 2) digital SOP and its fabrication for signal and power integrity, 3) optical SOP fabrication with embedded actives and passives, 4) RF SOP for high Q-embedded inductors, filters and other RF components, 5) mixed signal electrical test, 6) mixed signal reliability, and 7) demonstration of SOP by INC prototype system.

Colloidal processing of polymer ceramic nanocomposites for integral capacitors

Polymer ceramic composites form a suitable material system for low temperature fabrication of embedded capacitors appropriate for the MCM-L technology. Improved electrical properties such as permittivity can be achieved by efficient filling of polymers with high dielectric constant ceramic powders such as lead magnesium niobate-lead titanate (PMN-PT) and barium titanate (BT). Photodefinable epoxies as the matrix polymer allow fine feature definition of the capacitor elements by conventional lithography techniques. The optimum weight percent of dispersant is tuned by monitoring the viscosity of the suspension. The dispersion mechanism (steric and electrostatic contribution) in a slightly polar solvent such as propylene glycol methyl ether acetate (PGMEA) is investigated from electrophoretic measurements. A high positive zeta potential is observed in the suspension, which suggests a strong contribution of electrostatic stabilization. By optimizing the particle packing using a bimodal distribution and modified processing methodology, a dielectric constant greater than 135 was achieved in PMN-PT/epoxy system. Suspensions are made with the lowest PGMEA content to ensure the efficiency of the dispersion and efficient particle packing in the dried film. Improved colloidal processing of nanoparticle-filled epoxy is a promising method to obtain ultra-thin capacitor films (<2/spl mu/m) with high capacitance density and improved yield. Capacitance of 35 nF/cm/sup 2/ was achieved with the thinnest films (2.5-3.0 /spl mu/m).

High aspect ratio metal-polymer composite structures for nano interconnects

This paper presents a novel low-temperature process that combines high-aspect-ratio polymer structures with electroless copper plating to create laterally compliant MEMS structures. These structures are evaluated as IC-package interconnects that can lead to reliable, low-cost and high-performance nano wafer-level packaging. High-aspect-ratio low CTE polyimide structures with low stress, high toughness and strength were fabricated using plasma etching, This dry etching process was tuned to yield a wall angle above 80 degrees leading to an aspect ratio higher than 4. The etching process also leads to roughened sidewalls for selective electroless plating on the sidewalls of the polymer structures. Simulations of these fabricated structures show tremendous reduction in the stresses at the interfaces and superior reliability as IC-package nano interconnects. Metal-coated polymer structures from MEMS fabrication techniques can provide low-cost high-performance solutions for wafer-level-packaging.

New paradigm in IC package interconnections by reworkable nano-interconnects

We propose new IC packaging technologies that have the potential to bring about disruptive innovations in interconnect pitch, best electrical and mechanical properties, low-cost and chip size. Current approaches for chip to package interconnections are limited in terms of either pitch or electrical-mechanical trade-off properties. For example, lead free solder interconnects fail mechanically as the pitch is brought down from current 200 micron pitch to 20 micron. Compliant leads, on the other hand, solve mechanical reliability but at the expense of electrical performance. Solution-derived materials for reworkable nano-interconnects can be a viable technology to meet these two challenges. Nano-grained electroplated copper is chosen as the primary interconnect material. Compliancy was addressed by tuning the process to electroplate high-aspect-ratio structures. Reworkability was addressed by a thin, liquid lead-free solder interface between the interconnect and the package. Two approaches, sol-gel and electroless plating were used in this work to deposit these liquid interface films of lead free solders of the order of 50-300 nm. In the sol-gel process, metal-organic polymer solutions were heat-treated in a reducing atmosphere at 300/spl deg/C to form lead-free solders (Sn-Ag-Cu). In the other approach, lead-free alloy films were deposited from aqueous plating solutions consisting of suitable metal salts and reducing agents. This process was done at temperatures of 45/spl deg/C. The lead-free solder composition was controlled by altering the plating bath formulation. Lead-free solder films formed from both the above approaches were demonstrated to bond copper pads. Solution-derived nano-solder technology is an attractive low-cost method for bump-less nano-interconnects and other applications such as MEMS hermetic packaging and compliant interconnect bonding.

Embedded decoupling capacitor performance in high speed circuits

Embedded decoupling is normally considered a better solution than surface mount decoupling for suppressing the switching noise of a high speed digital board/package because of its shorter leads that result in smaller parasitic inductance. This leads to lower impedance over a higher frequency band. It is presumably better in reliability and lowers the cost as well. Designers tend to use large value capacitors for efficient decoupling. Usually, to increase capacitance of an embedded capacitor, one can use a material with higher dielectric constant, design larger electrodes, and reduce the thickness of the dielectric. However, these strategies may sometimes lead to lower performance at high frequency band. This paper will discuss the pros and cons of different embedded capacitor approaches through simulation. As an application example, a typical power/ground network with an embedded capacitor will be compared with that of surface mount discrete capacitor.

Design, modeling and characterization of embedded capacitor networks for mid-frequency decoupling in semiconductor systems

Embedded passives are gaining in importance due to the reduction in size of consumer electronic products. Among the passives, capacitors pose the biggest challenge due to the large capacitance required for decoupling high performance circuits. This paper focuses on the characterization and modeling of embedded capacitors. Design and modeling of embedded capacitor networks for decoupling semiconductor systems in the mid-frequency band (100 MHz to 2 GHz) will be highlighted in this paper

Development of high-k embedded capacitors on printed wiring board using sol-gel and foil-transfer processes

Sol-gel ceramic films were fabricated for organic system-on-package compatible integral capacitor applications. The films were synthesized on Ti and Ni foils which were then transferred onto organic boards using a lamination step. SrTiO/sub 3/ and BaTiO/sub 3/ films were synthesized with capacitance as high as 700 nF/cm/sup 2/ and loss as low as 0.005. It should be noted that the high permeability of Ni (approximately 100 in bulk form) and lower conductivity compared to copper decreases the skin depth and increases the resistivity of copper. This can have a deleterious effect on Q. More studies are underway to investigate this effect.

Electrochemical Biosensors and Microfluidics in Organic System-on-Package Technology

A nanobioelectronic system-on-package (SOP) with integrated electrochemical sensors, microfluidic channels and microneedles was demonstrated with organic compatible processes. A novel amperometric glucose sensor based on carbon nanotubes/glassy carbon working electrodes and glucose oxidase enzyme encapsulated in a sol-gel derived zirconia/nafion matrix was developed to demonstrate the biosensing. The sol-gel chemistry provides an attractive way to immobilize the sensitive biomolecules on the electrode at low temperatures. The amperometric measurements were carried out with a three-electrode system. SU8 epoxy based thick microfluidic channels were built over the electrode layer and then the enzyme was immobilized, followed by sealing of the channel with a PDMS membrane using a low temperature bonding process (60degC). The enzyme-catalyst reaction was recorded as the release of electrons from the oxidation of glucose into gluconolactone, hydrogen peroxide and subsequently into water. The results indicate that the response time is within few seconds. The current varied from 1 muA to 2.5 muA as the glucose concentration was increased from 5 mM to 20 mM. Finally, a compatible microneedle technology is demonstrated to enable transdermal fluid injection into the device for real-time health monitoring. Nanobio SOP with recent advances in nanobiosensing, nanomedicine, low-cost polymer-based high-density packaging, mixed-signal electronics can lead to the portable, reliable and cost effective biomedical devices of the future.

Evaluation of liquid crystal polymers for high performance SOP application

Electronic devices increasingly rely on new materials with improved properties such as lower coefficient of thermal expansion (preferably close to silicon), higher modulus, lower permittivity and dielectric loss, lower moisture absorption better thermal conductivity, higher dimensional stability, and most importantly reduced warpage particularly after the build-up process. Liquid crystal polymers (LCPs) have led to increasing interest for the packaging community due to their superior thermal and electrical properties. The targeted applications areas for LCPs are RF packaging, due to their low loss and low dielectric constant over a wide frequency range (Fukutake and Inoue, 2002; Fukutake, 1998; Jayaraj et al, 1995; Lawrence, 2000; Jayaraj et al, 1996; Yue et al, 1999,), near hermitic plastic sealing due to superior moisture barrier properties (Jayaraj et al, 1997), flex circuits and microvia laminates for high density interconnection (Corbett et al, 2000; Yue and Chan, 1998). This paper is focused toward possible application of LCP as a dielectric material for lamination on PWB and other engineered organic substrates. Commercially available LCP samples were analyzed using a variety of thermal analysis techniques. Based on thermal properties such as coefficient of thermal expansion (CTE), thermal degradation temperature and modulus, samples were selected for applications as a dielectric material. It is expected that a low CTE dielectric such as LCP will further reduce the dielectric film stress even when the CTE of the chip is matched with that of the substrate.

Integrating High-k Ceramic Thin Film Capacitors into Organic Substrates Via Low-Cost Solution Processing

Current organic package-compatible embedded decoupling capacitors are based on thick film (8-16 m) polymer-ceramic composites with dielectric constant (k) of 20-30 and do not have sufficient capacitance density to meet the impedance requirements for emerging high-speed circuits and high power density microprocessors. High-k/high capacitance density ceramics films that can meet the performance targets are generally deposited by high-temperature processing or costly vacuum technology (radio frequency sputtering, PECVD) which are expensive and also incompatible with organic packages. The objective of this project is to develop ultra thin films (100-300nm) with high dielectric constant using organic compatible processes to meet future decoupling applications. In the current study, direct deposition of crystalline ceramic films on organic boards at temperatures less than 100C was demonstrated with the hydrothermal method. Post-hydrothermal treatments were shown to minimize the defects in the as-synthesized hydrothermal barium titanate films and improve the breakdown voltage (BDV) and leakage characteristics. Thin films with high capacitance densities and breakdown voltages of 10V were demonstrated. As an alternate technique, sol-gel technology was also demonstrated to integrate ceramic thin films in organic packages. A major barrier to synthesis of sol-gel films on copper foils is the process incompatibility of the sol-gel barium titanate with the copper electrodes. To enable process compatibility, process variables like sol pyrolysis temperature and time, and sintering conditions/atmosphere were optimized. Capacitance densities above 1.1F/cm was demonstrated on commercial copper foils with a BDV above 10 V. The two technologies reported in this study can potentially meet midfrequency decoupling requirements of digital systems.