Mako Kobayashi

Semiconductor memory device capable of increasing chip yields while maintaining rapid operation

Substrate bias voltage generating circuit

Multi-bank clock synchronous type semiconductor memory device having improved memory array and power supply arrangement

High speed operable semiconductor memory device with memory blocks arranged about the center

Constant internal voltage generation circuit

Substrate voltage generating circuit provided with a transistor having a thin gate oxide film and a semiconductor integrated circuit device provided with the same

Voltage converting circuit allowing control of current drivability in accordance with operational frequency

Semiconductor memory device capable of performing stable operation for noise while preventing increase in chip area

Semiconductor device including internal potential generating circuit allowing tuning in short period of time and reduction of chip area

Semiconductor device including voltage down converter allowing tuning in short period of time and reduction of chip area