Takahiro Tsuruda

An SOI-DRAM with wide operating voltage range by CMOS/SIMOX technology

For future ULSI DRAMs beyond the 256 Mb generation, several circuit techniques and memory cell structures have been proposed to meet the requirement of high performance at low voltage. These solutions frequently involve complicated processing steps and/or the ultimate limitations of current Si-MOS devices. DRAM on silicon on insulator (SOI) substrate is a more simple solution to the problem. Thin-film SOI structures with isolation by implanted oxygen (SIMOX) process are under investigation for SRAM and logic. A SOI-DRAM test device with 100 nm thick SOI film has been fabricated in 0.5 /spl mu/m CMOS/SIMOX technology. With this 64 kb SOI-DRAM the bit-line to memory cell capacitance ratio Cb/Cs is reduced by 25% compared with the reference bulk-Si DRAM, because of the decreased junction capacitance. RAS access time tRAC is 70 ns at 2.7 VVcc, as fast as the equivalent bulk-Si device at 4 VVcc. The clock timing in this DRAM is not optimized, so access time should improve with well-tuned clocks. The boosted-level generator with body-contact structure enhances the upper Vcc margin and the reduced body-effect of sense-amplifier transistors improves the lower Vcc margin. The SOI-DRAM has an operating Vcc range from 2.3 V to 4.0 V. >

SOI-DRAM circuit technologies for low power high speed multigiga scale memories

This paper describes a silicon on insulator (SOI) DRAM which has a body bias controlling technique for high-speed circuit operation and a new type of redundancy for low standby power operation, aimed at high yield. The body bias controlling technique contributes to super-body synchronous sensing and body-bias controlled logic. The super-body synchronous sensing achieves 3.0 ns faster sensing than body synchronous sensing and the body-bias controlled logic realizes 8.0 ns faster peripheral logic operation compared with a conventional logic scheme, at 1.5 V in a 4 Gb-level SOI DRAM. The body-bias controlled logic also realizes a body-bias change current reduction of 1/20, compared with a bulk well-structure. A new type of redundancy that overcomes the standby current failure resulting from a wordline-bitline short is also discussed in respect of yield and area penalty.

Low voltage circuit design techniques for battery-operated and/or giga-scale DRAMs

This paper describes a charge-transferred well (CTW) sensing method for high-speed array circuit operation and a level-controllable local power line (LCL) structure for high-speed/low-power operation of peripheral logic circuits, aimed at low voltage operating and/or giga-scale DRAMs. The CTW method achieves 19% faster sensing and the LCL structure realizes 42% faster peripheral logic operation than the conventional scheme, at 1.2 V in 15 Mb-level devices. The LCL structure realizes a subthreshold leakage current reduction of three or four orders of magnitude in sleep mode, compared with a conventional hierarchical power line structure. A negative-voltage word line technique that overcomes the refresh degradation resulting from reduced storage charge (Q/sub s/) at low voltage operation for improved reliability is also discussed. An experimental 1.2 V 16 Mb DRAM with a RAS access time of 49 ns has been successfully developed using these technologies and a 0.4-/spl mu/m CMOS process. The chip size is 7.9/spl times/16.7 mm/sup 2/ and cell size is 1.35/spl times/2.8 /spl mu/m/sup 2/.

ULSI DRAM/SIMOX with stacked capacitor cells for low-voltage operation

An SOI-DRAM test device was fabricated on thin-film SOI (Silicon On Insulator) structure with 0.5 /spl mu/m CMOS/SIMOX (Separation by IMplanted OXygen) technology. Field-shield isolation and polysilicon pad techniques were introduced for the specific problems to thin-film SOI devices such as the floating body effects and increase of parasitic source/drain resistance, respectively. Keeping the thin-film SOI from etching off during DRAM cell processing was especially cared by using high-selectivity ECR etching technology. The bit-line capacitance of the experimental SOI-DRAM is reduced by 25% and the /RAS access time is 30% faster compared with the equivalent Bulk-Si DRAM. Low voltage DRAM operation down to 2 V range is also observed.<<ETX>>

High-speed/high-bandwidth design methodologies for on-chip DRAM core multimedia system LSI's

Recently, as multimedia large scale integrated devices (LSIs) have developed, there has been strongly increased demand for high-speed/high-bandwidth LSIs which integrate the DRAM core and logic elements (CPU etc.). However, the high-speed/high-bandwidth operation induces the large switching noise. This noise degrades the DRAMs operating margin, and especially its data retention characteristics. In this paper, we analyze the noise transmission model and propose DRAM and logic compatible design methodologies to maintain the reliability of high-speed/high-bandwidth system LSIs. We also show that good experimental results are obtained on the test device. Furthermore, we propose the most suitable V/sub DD//GND line scheme for on-chip DRAM system LSI.

SOI-DRAM circuit technologies for low power high speed multi-giga scale memories

New SOI-DRAM circuits were proposed and described. The body bias controlling technique, especially super body-synchronous sensing, is found to be suitable for low voltage operation. A new type of redundancy enables Icc2 reduction and promises high yield against the increasing standby current failure.

High-speed/high-band width design methodologies for on chip DRAM core multimedia system LSIs

Recently, as multimedia LSIs have developed, the demand for high-speed/high-band width LSIs which integrate the DRAM core and logic elements (CPU etc.) have been strongly required. However, the high-speed/high-band width operation induces the large switching noise. This noise degrades a DRAMs operating margin, and especially the data retention characteristics. In this paper, we analyze the noise transmission model and propose a DRAM and logic compatible design methodology to maintain the reliability of high-speed/high-band width system LSIs. Good experimental results are obtained on the test device.